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git01.mediatek.com / filogic / uboot / da26f81524ac3d72545e2b688aee8e73aa0e965a / . / board / engicam / imx6ul / imx6ul.c
blob: 24d654445dbd8569a6b85b1d1fbd6b69b0c1ca46 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Jagan Teki72e57502016-12-13 17:56:52 +0100[diff] [blame]2/*
3 * Copyright (C) 2016 Amarula Solutions B.V.
4 * Copyright (C) 2016 Engicam S.r.l.
5 * Author: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki72e57502016-12-13 17:56:52 +0100[diff] [blame]6 */
7
Jagan Teki515bd002017-11-21 00:02:16 +0530[diff] [blame]8#include <mmc.h>
Jagan Teki72e57502016-12-13 17:56:52 +0100[diff] [blame]9
10#include <asm/io.h>
11#include <asm/gpio.h>
12#include <linux/sizes.h>
13
14#include <asm/arch/clock.h>
Jagan Teki55c495c2016-12-13 17:56:55 +0100[diff] [blame]15#include <asm/arch/crm_regs.h>
Jagan Teki72e57502016-12-13 17:56:52 +0100[diff] [blame]16#include <asm/arch/iomux.h>
17#include <asm/arch/mx6-pins.h>
18#include <asm/arch/sys_proto.h>
Stefano Babic33731bc2017-06-29 10:16:06 +0200[diff] [blame]19#include <asm/mach-imx/iomux-v3.h>
Jagan Teki72e57502016-12-13 17:56:52 +0100[diff] [blame]20
Jagan Tekic5d86812017-05-07 02:43:14 +0530[diff] [blame]21#include "../common/board.h"
22
Jagan Teki55c495c2016-12-13 17:56:55 +0100[diff] [blame]23#ifdef CONFIG_NAND_MXS
24
25#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
26#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
27 PAD_CTL_SRE_FAST)
28#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
29
30static iomux_v3_cfg_t const nand_pads[] = {
Jagan Teki89395642017-05-07 02:43:09 +0530[diff] [blame]31 IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
32 IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
33 IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
34 IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
35 IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
36 IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
37 IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
38 IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
39 IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
40 IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
41 IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
42 IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
43 IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
44 IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
45 IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
Jagan Teki55c495c2016-12-13 17:56:55 +0100[diff] [blame]46};
47
Jagan Tekic5d86812017-05-07 02:43:14 +0530[diff] [blame]48void setup_gpmi_nand(void)
Jagan Teki55c495c2016-12-13 17:56:55 +0100[diff] [blame]49{
50 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
51
52 /* config gpmi nand iomux */
Jagan Teki89395642017-05-07 02:43:09 +0530[diff] [blame]53 SETUP_IOMUX_PADS(nand_pads);
Jagan Teki55c495c2016-12-13 17:56:55 +0100[diff] [blame]54
55 clrbits_le32(&mxc_ccm->CCGR4,
56 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
57 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
58 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
59 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
60 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
61
62 /*
63 * config gpmi and bch clock to 100 MHz
64 * bch/gpmi select PLL2 PFD2 400M
65 * 100M = 400M / 4
66 */
67 clrbits_le32(&mxc_ccm->cscmr1,
68 MXC_CCM_CSCMR1_BCH_CLK_SEL |
69 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
70 clrsetbits_le32(&mxc_ccm->cscdr1,
71 MXC_CCM_CSCDR1_BCH_PODF_MASK |
72 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
73 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
74 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
75
76 /* enable gpmi and bch clock gating */
77 setbits_le32(&mxc_ccm->CCGR4,
78 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
79 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
80 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
81 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
82 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
83
84 /* enable apbh clock gating */
85 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
86}
87#endif /* CONFIG_NAND_MXS */
Jagan Teki515bd002017-11-21 00:02:16 +0530[diff] [blame]88
89#ifdef CONFIG_ENV_IS_IN_MMC
90int board_mmc_get_env_dev(int devno)
91{
92 /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
93 return (devno == 0) ? 0 : 1;
94}
95#endif