Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 1 | /* |
| 2 | * board/renesas/ulcb/ulcb.c |
| 3 | * This file is ULCB board support. |
| 4 | * |
| 5 | * Copyright (C) 2017 Renesas Electronics Corporation |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <malloc.h> |
| 12 | #include <netdev.h> |
| 13 | #include <dm.h> |
| 14 | #include <dm/platform_data/serial_sh.h> |
| 15 | #include <asm/processor.h> |
| 16 | #include <asm/mach-types.h> |
| 17 | #include <asm/io.h> |
| 18 | #include <linux/errno.h> |
| 19 | #include <asm/arch/sys_proto.h> |
| 20 | #include <asm/gpio.h> |
| 21 | #include <asm/arch/gpio.h> |
| 22 | #include <asm/arch/rmobile.h> |
| 23 | #include <asm/arch/rcar-mstp.h> |
| 24 | #include <asm/arch/sh_sdhi.h> |
| 25 | #include <i2c.h> |
| 26 | #include <mmc.h> |
| 27 | |
| 28 | DECLARE_GLOBAL_DATA_PTR; |
| 29 | |
| 30 | #define CPGWPCR 0xE6150904 |
| 31 | #define CPGWPR 0xE615090C |
| 32 | |
| 33 | #define CLK2MHZ(clk) (clk / 1000 / 1000) |
| 34 | void s_init(void) |
| 35 | { |
| 36 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
| 37 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
| 38 | |
| 39 | /* Watchdog init */ |
| 40 | writel(0xA5A5A500, &rwdt->rwtcsra); |
| 41 | writel(0xA5A5A500, &swdt->swtcsra); |
| 42 | |
| 43 | writel(0xA5A50000, CPGWPCR); |
| 44 | writel(0xFFFFFFFF, CPGWPR); |
| 45 | } |
| 46 | |
| 47 | #define GSX_MSTP112 BIT(12) /* 3DG */ |
| 48 | #define TMU0_MSTP125 BIT(25) /* secure */ |
| 49 | #define TMU1_MSTP124 BIT(24) /* non-secure */ |
| 50 | #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 51 | #define DVFS_MSTP926 BIT(26) |
Marek Vasut | cea5c8f | 2017-09-12 19:07:22 +0200 | [diff] [blame] | 52 | #define HSUSB_MSTP704 BIT(4) /* HSUSB */ |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 53 | |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 54 | int board_early_init_f(void) |
| 55 | { |
| 56 | /* TMU0,1 */ /* which use ? */ |
| 57 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 58 | |
| 59 | #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
| 60 | /* DVFS for reset */ |
| 61 | mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); |
| 62 | #endif |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | /* SYSC */ |
| 67 | /* R/- 32 Power status register 2(3DG) */ |
| 68 | #define SYSC_PWRSR2 0xE6180100 |
| 69 | /* -/W 32 Power resume control register 2 (3DG) */ |
| 70 | #define SYSC_PWRONCR2 0xE618010C |
| 71 | |
Marek Vasut | cea5c8f | 2017-09-12 19:07:22 +0200 | [diff] [blame] | 72 | /* HSUSB block registers */ |
| 73 | #define HSUSB_REG_LPSTS 0xE6590102 |
| 74 | #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) |
| 75 | #define HSUSB_REG_UGCTRL2 0xE6590184 |
| 76 | #define HSUSB_REG_UGCTRL2_USB0SEL 0x30 |
| 77 | #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 |
| 78 | |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 79 | int board_init(void) |
| 80 | { |
| 81 | /* adress of boot parameters */ |
| 82 | gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
| 83 | |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 84 | /* USB1 pull-up */ |
| 85 | setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); |
| 86 | |
Marek Vasut | cea5c8f | 2017-09-12 19:07:22 +0200 | [diff] [blame] | 87 | /* Configure the HSUSB block */ |
| 88 | mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); |
| 89 | /* Choice USB0SEL */ |
| 90 | clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, |
| 91 | HSUSB_REG_UGCTRL2_USB0SEL_EHCI); |
| 92 | /* low power status */ |
| 93 | setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); |
| 94 | |
Marek Vasut | 7cf1c7f | 2017-08-20 17:13:48 +0200 | [diff] [blame] | 95 | return 0; |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 96 | } |
Marek Vasut | ad43cd3 | 2017-07-21 23:15:21 +0200 | [diff] [blame] | 97 | |
| 98 | int dram_init(void) |
| 99 | { |
| 100 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
| 101 | #if (CONFIG_NR_DRAM_BANKS >= 2) |
| 102 | gd->ram_size += PHYS_SDRAM_2_SIZE; |
| 103 | #endif |
| 104 | #if (CONFIG_NR_DRAM_BANKS >= 3) |
| 105 | gd->ram_size += PHYS_SDRAM_3_SIZE; |
| 106 | #endif |
| 107 | #if (CONFIG_NR_DRAM_BANKS >= 4) |
| 108 | gd->ram_size += PHYS_SDRAM_4_SIZE; |
| 109 | #endif |
| 110 | |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | int dram_init_banksize(void) |
| 115 | { |
| 116 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 117 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 118 | #if (CONFIG_NR_DRAM_BANKS >= 2) |
| 119 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
| 120 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
| 121 | #endif |
| 122 | #if (CONFIG_NR_DRAM_BANKS >= 3) |
| 123 | gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
| 124 | gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
| 125 | #endif |
| 126 | #if (CONFIG_NR_DRAM_BANKS >= 4) |
| 127 | gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
| 128 | gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
| 129 | #endif |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | const struct rmobile_sysinfo sysinfo = { |
| 134 | CONFIG_RCAR_BOARD_STRING |
| 135 | }; |