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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Yand6e658c2017-06-01 18:01:31 +08002/*
3 * (C)Copyright 2016 Rockchip Electronics Co., Ltd
4 * Authors: Andy Yan <andy.yan@rock-chips.com>
Andy Yand6e658c2017-06-01 18:01:31 +08005 */
6
7#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Kever Yangf6b6d942020-02-19 09:46:06 +08009#include <syscon.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/global_data.h>
Kever Yangf6b6d942020-02-19 09:46:06 +080011#include <asm/arch-rockchip/clock.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080012#include <asm/arch-rockchip/grf_rv1108.h>
13#include <asm/arch-rockchip/hardware.h>
Andy Yand6e658c2017-06-01 18:01:31 +080014
15DECLARE_GLOBAL_DATA_PTR;
16
Kever Yang8fdd8882020-04-13 09:38:30 +080017int board_early_init_f(void)
Andy Yand6e658c2017-06-01 18:01:31 +080018{
Andy Yand6e658c2017-06-01 18:01:31 +080019 struct rv1108_grf *grf;
David Wu5a04e0c2018-01-13 13:53:57 +080020 enum {
21 GPIO3C3_SHIFT = 6,
22 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
23
24 GPIO3C2_SHIFT = 4,
25 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
26
27 GPIO2D2_SHIFT = 4,
28 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
29 GPIO2D2_GPIO = 0,
30 GPIO2D2_UART2_SOUT_M0,
31
32 GPIO2D1_SHIFT = 2,
33 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
34 GPIO2D1_GPIO = 0,
35 GPIO2D1_UART2_SIN_M0,
36 };
Andy Yand6e658c2017-06-01 18:01:31 +080037
Kever Yangf6b6d942020-02-19 09:46:06 +080038 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
Andy Yand6e658c2017-06-01 18:01:31 +080039
40 /*evb board use UART2 m0 for debug*/
41 rk_clrsetreg(&grf->gpio2d_iomux,
42 GPIO2D2_MASK | GPIO2D1_MASK,
43 GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
44 GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
45 rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
46
47 return 0;
48}
49
Andy Yand6e658c2017-06-01 18:01:31 +080050int dram_init(void)
51{
52 gd->ram_size = 0x8000000;
53
54 return 0;
55}