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git01.mediatek.com / filogic / uboot / d9d727ad8e484970cd706fea63d91552c06745f7 / . / arch / arm / include / asm / arch-sunxi / cpu_sun9i.h
blob: 73de4707c16282a95b19e624eb8d1321bacae418 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]2/*
3 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
4 * (C) Copyright 2007-2013
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Jerry Wang <wangflord@allwinnertech.com>
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]7 */
8
9#ifndef _SUNXI_CPU_SUN9I_H
10#define _SUNXI_CPU_SUN9I_H
11
12#define REGS_AHB0_BASE 0x01C00000
13#define REGS_AHB1_BASE 0x00800000
14#define REGS_AHB2_BASE 0x03000000
15#define REGS_APB0_BASE 0x06000000
16#define REGS_APB1_BASE 0x07000000
17#define REGS_RCPUS_BASE 0x08000000
18
19#define SUNXI_SRAM_D_BASE 0x08100000
20
21/* AHB0 Module */
22#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]23
Philipp Tomsich3015e042016-10-28 18:21:29 +0800[diff] [blame]24#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
Chen-Yu Tsaia7c455f2016-10-28 18:21:35 +0800[diff] [blame]25/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */
26#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200)
Philipp Tomsich3015e042016-10-28 18:21:29 +0800[diff] [blame]27
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]28#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000)
29#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000)
30#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000)
31#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000)
32#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000)
33
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]34#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000)
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]35
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800[diff] [blame]36#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000)
37#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000)
38#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000)
39#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000)
40#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000)
41
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]42#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]43#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]44#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
45#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
46#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]47#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000)
48
49/* APB0 Module */
50#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]51#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
52#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]53
54/* APB1 Module */
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]55#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800)
56#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00)
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]57
58/* RCPUS Module */
Hans de Goede8760c912015-01-26 16:46:43 +0100[diff] [blame]59#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
Hans de Goede8760c912015-01-26 16:46:43 +0100[diff] [blame]60#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]61
Hans de Goeded20e35f2015-01-13 19:22:21 +0100[diff] [blame]62#ifndef __ASSEMBLY__
63void sunxi_board_init(void);
64void sunxi_reset(void);
65int sunxi_get_sid(unsigned int *sid);
66#endif
67
68#endif /* _SUNXI_CPU_SUN9I_H */