| Hans de Goede | d20e35f | 2015-01-13 19:22:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> |
| 3 | * (C) Copyright 2007-2013 |
| 4 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 5 | * Jerry Wang <wangflord@allwinnertech.com> |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef _SUNXI_CPU_SUN9I_H |
| 11 | #define _SUNXI_CPU_SUN9I_H |
| 12 | |
| 13 | #define REGS_AHB0_BASE 0x01C00000 |
| 14 | #define REGS_AHB1_BASE 0x00800000 |
| 15 | #define REGS_AHB2_BASE 0x03000000 |
| 16 | #define REGS_APB0_BASE 0x06000000 |
| 17 | #define REGS_APB1_BASE 0x07000000 |
| 18 | #define REGS_RCPUS_BASE 0x08000000 |
| 19 | |
| 20 | #define SUNXI_SRAM_D_BASE 0x08100000 |
| 21 | |
| 22 | /* AHB0 Module */ |
| 23 | #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) |
| 24 | #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) |
| 25 | |
| 26 | #define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000) |
| 27 | #define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000) |
| 28 | #define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000) |
| 29 | #define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) |
| 30 | #define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) |
| 31 | |
| 32 | #define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) |
| 33 | #define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) |
| 34 | #define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) |
| 35 | #define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) |
| 36 | |
| 37 | #define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) |
| 38 | #define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) |
| 39 | #define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) |
| 40 | |
| Philipp Tomsich | d36af1c | 2016-10-28 18:21:28 +0800 | [diff] [blame^] | 41 | #define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) |
| 42 | #define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) |
| 43 | #define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000) |
| 44 | #define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) |
| 45 | #define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) |
| 46 | |
| Hans de Goede | d20e35f | 2015-01-13 19:22:21 +0100 | [diff] [blame] | 47 | /* AHB1 Module */ |
| 48 | #define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) |
| 49 | #define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) |
| 50 | #define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) |
| 51 | #define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) |
| 52 | #define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) |
| 53 | |
| 54 | /* AHB2 Module */ |
| 55 | #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) |
| 56 | #define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) |
| 57 | #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) |
| 58 | #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) |
| 59 | #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) |
| 60 | |
| 61 | #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) |
| 62 | #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) |
| 63 | #define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) |
| 64 | |
| 65 | #define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) |
| 66 | #define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) |
| 67 | #define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) |
| 68 | #define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) |
| 69 | |
| 70 | #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) |
| 71 | #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) |
| 72 | #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) |
| 73 | #define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) |
| 74 | /* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ |
| 75 | #define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) |
| 76 | #define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) |
| 77 | |
| 78 | /* APB0 Module */ |
| 79 | #define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) |
| 80 | #define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) |
| 81 | #define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) |
| Hans de Goede | d20e35f | 2015-01-13 19:22:21 +0100 | [diff] [blame] | 82 | #define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) |
| 83 | #define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) |
| 84 | #define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) |
| 85 | |
| 86 | /* APB1 Module */ |
| 87 | #define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) |
| 88 | #define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) |
| 89 | #define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) |
| 90 | #define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) |
| 91 | #define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) |
| 92 | #define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) |
| 93 | #define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) |
| 94 | #define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) |
| 95 | #define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) |
| 96 | #define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) |
| 97 | #define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) |
| 98 | |
| 99 | /* RCPUS Module */ |
| Hans de Goede | 8760c91 | 2015-01-26 16:46:43 +0100 | [diff] [blame] | 100 | #define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) |
| Hans de Goede | d20e35f | 2015-01-13 19:22:21 +0100 | [diff] [blame] | 101 | #define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) |
| Hans de Goede | 8760c91 | 2015-01-26 16:46:43 +0100 | [diff] [blame] | 102 | #define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) |
| 103 | #define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) |
| Hans de Goede | d20e35f | 2015-01-13 19:22:21 +0100 | [diff] [blame] | 104 | |
| 105 | /* Misc. */ |
| 106 | #define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ |
| 107 | #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) |
| 108 | |
| 109 | #ifndef __ASSEMBLY__ |
| 110 | void sunxi_board_init(void); |
| 111 | void sunxi_reset(void); |
| 112 | int sunxi_get_sid(unsigned int *sid); |
| 113 | #endif |
| 114 | |
| 115 | #endif /* _SUNXI_CPU_SUN9I_H */ |