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git01.mediatek.com / filogic / uboot / d942f97328083f42d1f86cb75a5a5304ae36ee2a / . / arch / arm / dts / imxrt1170-evk-u-boot.dtsi
blob: 6e892c1af769c27ebac7a290bc630eddc915abae [file] [log] [blame]
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2022
4 * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
5 * Giulio Benetti <giulio.benetti@benettiengineering.com>
6 */
7
8/ {
Jesse Taube9fcbb552024-02-19 18:00:59 -0500[diff] [blame]9 binman: binman {
10 multiple-images;
11 };
12
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]13 chosen {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]14 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]15 };
16
17 clocks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]19 };
20
21 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]23 };
24};
25
26&osc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]28};
29
30&rcosc16M {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]32};
33
34&osc32k {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]36};
37
38&clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]40};
41
42&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]44};
45
46&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]48};
49
50&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]52};
53
54&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]56};
57
58&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]60};
61
62&gpt1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]64};
65
66&lpuart1 { /* console */
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]68};
69
70&semc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]72
73 bank1: bank@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]75 };
76};
77
78&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]80
81 imxrt1170-evk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]83 pinctrl_lpuart1: lpuart1grp {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]85 };
86
87 pinctrl_usdhc0: usdhc0grp {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]89 };
90 pinctrl_semc: semcgrp {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]92 };
93 };
94};
95
96&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]98};