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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / arm / dts / imxrt1170-evk-u-boot.dtsi
blob: f923a14301403ef2bbcd169f5d5eddc6c4dbe453 [file] [log] [blame]
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2022
4 * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
5 * Giulio Benetti <giulio.benetti@benettiengineering.com>
6 */
7
8/ {
9 chosen {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]10 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]11 };
12
13 clocks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]14 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]15 };
16
17 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]18 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]19 };
20};
21
22&osc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]23 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]24};
25
26&rcosc16M {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]27 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]28};
29
30&osc32k {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]31 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]32};
33
34&clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]35 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]36};
37
38&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]39 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]40};
41
42&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]43 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]44};
45
46&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]47 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]48};
49
50&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]51 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]52};
53
54&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]55 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]56};
57
58&gpt1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]59 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]60};
61
62&lpuart1 { /* console */
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]63 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]64};
65
66&semc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]67 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]68
69 bank1: bank@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]70 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]71 };
72};
73
74&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]75 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]76
77 imxrt1170-evk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]78 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]79 pinctrl_lpuart1: lpuart1grp {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]80 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]81 };
82
83 pinctrl_usdhc0: usdhc0grp {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]84 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]85 };
86 pinctrl_semc: semcgrp {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]87 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]88 };
89 };
90};
91
92&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]93 bootph-pre-ram;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]94};