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Michal Simek04b7e622015-01-15 10:01:51 +01001/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/arch/hardware.h>
10#include <asm/arch/sys_proto.h>
Alexander Graf0e2088c2016-03-04 01:09:49 +010011#include <asm/armv8/mmu.h>
Michal Simek04b7e622015-01-15 10:01:51 +010012#include <asm/io.h>
13
14#define ZYNQ_SILICON_VER_MASK 0xF000
15#define ZYNQ_SILICON_VER_SHIFT 12
16
17DECLARE_GLOBAL_DATA_PTR;
18
Alexander Graf0e2088c2016-03-04 01:09:49 +010019static struct mm_region zynqmp_mem_map[] = {
20 {
York Sunc7104e52016-06-24 16:46:22 -070021 .virt = 0x0UL,
22 .phys = 0x0UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010023 .size = 0x80000000UL,
24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
25 PTE_BLOCK_INNER_SHARE
26 }, {
York Sunc7104e52016-06-24 16:46:22 -070027 .virt = 0x80000000UL,
28 .phys = 0x80000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010029 .size = 0x70000000UL,
30 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
31 PTE_BLOCK_NON_SHARE |
32 PTE_BLOCK_PXN | PTE_BLOCK_UXN
33 }, {
York Sunc7104e52016-06-24 16:46:22 -070034 .virt = 0xf8000000UL,
35 .phys = 0xf8000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010036 .size = 0x07e00000UL,
37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
38 PTE_BLOCK_NON_SHARE |
39 PTE_BLOCK_PXN | PTE_BLOCK_UXN
40 }, {
York Sunc7104e52016-06-24 16:46:22 -070041 .virt = 0x400000000UL,
42 .phys = 0x400000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010043 .size = 0x200000000UL,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
45 PTE_BLOCK_NON_SHARE |
46 PTE_BLOCK_PXN | PTE_BLOCK_UXN
47 }, {
York Sunc7104e52016-06-24 16:46:22 -070048 .virt = 0x600000000UL,
49 .phys = 0x600000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010050 .size = 0x800000000UL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
52 PTE_BLOCK_INNER_SHARE
53 }, {
York Sunc7104e52016-06-24 16:46:22 -070054 .virt = 0xe00000000UL,
55 .phys = 0xe00000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010056 .size = 0xf200000000UL,
57 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
58 PTE_BLOCK_NON_SHARE |
59 PTE_BLOCK_PXN | PTE_BLOCK_UXN
60 }, {
61 /* List terminator */
62 0,
63 }
64};
65struct mm_region *mem_map = zynqmp_mem_map;
66
Michal Simek1a2d5e22016-05-30 10:41:26 +020067u64 get_page_table_size(void)
68{
69 return 0x14000;
70}
71
Michal Simekc23d3f82015-11-05 08:34:35 +010072static unsigned int zynqmp_get_silicon_version_secure(void)
73{
74 u32 ver;
75
76 ver = readl(&csu_base->version);
77 ver &= ZYNQMP_SILICON_VER_MASK;
78 ver >>= ZYNQMP_SILICON_VER_SHIFT;
79
80 return ver;
81}
82
Michal Simek04b7e622015-01-15 10:01:51 +010083unsigned int zynqmp_get_silicon_version(void)
84{
Michal Simekc23d3f82015-11-05 08:34:35 +010085 if (current_el() == 3)
86 return zynqmp_get_silicon_version_secure();
87
Michal Simek04b7e622015-01-15 10:01:51 +010088 gd->cpu_clk = get_tbclk();
89
90 switch (gd->cpu_clk) {
Michal Simek0ca55572015-04-15 14:59:19 +020091 case 0 ... 1000000:
92 return ZYNQMP_CSU_VERSION_VELOCE;
Michal Simek04b7e622015-01-15 10:01:51 +010093 case 50000000:
94 return ZYNQMP_CSU_VERSION_QEMU;
Michal Simek8d2c02d2015-08-20 14:01:39 +020095 case 4000000:
96 return ZYNQMP_CSU_VERSION_EP108;
Michal Simek04b7e622015-01-15 10:01:51 +010097 }
98
Michal Simek8d2c02d2015-08-20 14:01:39 +020099 return ZYNQMP_CSU_VERSION_SILICON;
Michal Simek04b7e622015-01-15 10:01:51 +0100100}