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Michal Simek04b7e622015-01-15 10:01:51 +01001/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/arch/hardware.h>
10#include <asm/arch/sys_proto.h>
Alexander Graf0e2088c2016-03-04 01:09:49 +010011#include <asm/armv8/mmu.h>
Michal Simek04b7e622015-01-15 10:01:51 +010012#include <asm/io.h>
13
14#define ZYNQ_SILICON_VER_MASK 0xF000
15#define ZYNQ_SILICON_VER_SHIFT 12
16
17DECLARE_GLOBAL_DATA_PTR;
18
Alexander Graf0e2088c2016-03-04 01:09:49 +010019static struct mm_region zynqmp_mem_map[] = {
20 {
21 .base = 0x0UL,
22 .size = 0x80000000UL,
23 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
24 PTE_BLOCK_INNER_SHARE
25 }, {
26 .base = 0x80000000UL,
27 .size = 0x70000000UL,
28 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
29 PTE_BLOCK_NON_SHARE |
30 PTE_BLOCK_PXN | PTE_BLOCK_UXN
31 }, {
32 .base = 0xf8000000UL,
33 .size = 0x07e00000UL,
34 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
35 PTE_BLOCK_NON_SHARE |
36 PTE_BLOCK_PXN | PTE_BLOCK_UXN
37 }, {
38 .base = 0xffe00000UL,
39 .size = 0x00200000UL,
40 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
41 PTE_BLOCK_INNER_SHARE
42 }, {
43 .base = 0x400000000UL,
44 .size = 0x200000000UL,
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 }, {
49 .base = 0x600000000UL,
50 .size = 0x800000000UL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
52 PTE_BLOCK_INNER_SHARE
53 }, {
54 .base = 0xe00000000UL,
55 .size = 0xf200000000UL,
56 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
57 PTE_BLOCK_NON_SHARE |
58 PTE_BLOCK_PXN | PTE_BLOCK_UXN
59 }, {
60 /* List terminator */
61 0,
62 }
63};
64struct mm_region *mem_map = zynqmp_mem_map;
65
Michal Simek1a2d5e22016-05-30 10:41:26 +020066u64 get_page_table_size(void)
67{
68 return 0x14000;
69}
70
Michal Simekc23d3f82015-11-05 08:34:35 +010071static unsigned int zynqmp_get_silicon_version_secure(void)
72{
73 u32 ver;
74
75 ver = readl(&csu_base->version);
76 ver &= ZYNQMP_SILICON_VER_MASK;
77 ver >>= ZYNQMP_SILICON_VER_SHIFT;
78
79 return ver;
80}
81
Michal Simek04b7e622015-01-15 10:01:51 +010082unsigned int zynqmp_get_silicon_version(void)
83{
Michal Simekc23d3f82015-11-05 08:34:35 +010084 if (current_el() == 3)
85 return zynqmp_get_silicon_version_secure();
86
Michal Simek04b7e622015-01-15 10:01:51 +010087 gd->cpu_clk = get_tbclk();
88
89 switch (gd->cpu_clk) {
Michal Simek0ca55572015-04-15 14:59:19 +020090 case 0 ... 1000000:
91 return ZYNQMP_CSU_VERSION_VELOCE;
Michal Simek04b7e622015-01-15 10:01:51 +010092 case 50000000:
93 return ZYNQMP_CSU_VERSION_QEMU;
Michal Simek8d2c02d2015-08-20 14:01:39 +020094 case 4000000:
95 return ZYNQMP_CSU_VERSION_EP108;
Michal Simek04b7e622015-01-15 10:01:51 +010096 }
97
Michal Simek8d2c02d2015-08-20 14:01:39 +020098 return ZYNQMP_CSU_VERSION_SILICON;
Michal Simek04b7e622015-01-15 10:01:51 +010099}