Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 1249065 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 2 | /* |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 3 | * (C) Copyright 2008 - 2015 Michal Simek <monstr@monstr.eu> |
Michal Simek | 403d619 | 2008-07-11 10:10:31 +0200 | [diff] [blame] | 4 | * Clean driver and add xilinx constant from header file |
wdenk | 1249065 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 5 | * |
Michal Simek | 403d619 | 2008-07-11 10:10:31 +0200 | [diff] [blame] | 6 | * (C) Copyright 2004 Atmark Techno, Inc. |
wdenk | 1249065 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 7 | * Yasushi SHOJI <yashi@atmark-techno.com> |
wdenk | 1249065 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <config.h> |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 11 | #include <common.h> |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 12 | #include <dm.h> |
Michal Simek | 403d619 | 2008-07-11 10:10:31 +0200 | [diff] [blame] | 13 | #include <asm/io.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 14 | #include <linux/bitops.h> |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 15 | #include <linux/compiler.h> |
| 16 | #include <serial.h> |
wdenk | 1249065 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 17 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 18 | #define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */ |
| 19 | #define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */ |
| 20 | #define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */ |
| 21 | #define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */ |
wdenk | 1249065 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 22 | |
Michal Simek | e5b3c1d | 2014-01-21 07:29:47 +0100 | [diff] [blame] | 23 | #define ULITE_CONTROL_RST_TX 0x01 |
| 24 | #define ULITE_CONTROL_RST_RX 0x02 |
| 25 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 26 | static bool little_endian; |
| 27 | |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 28 | struct uartlite { |
| 29 | unsigned int rx_fifo; |
| 30 | unsigned int tx_fifo; |
| 31 | unsigned int status; |
Michal Simek | e5b3c1d | 2014-01-21 07:29:47 +0100 | [diff] [blame] | 32 | unsigned int control; |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 33 | }; |
| 34 | |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 35 | struct uartlite_plat { |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 36 | struct uartlite *regs; |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 37 | }; |
| 38 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 39 | static u32 uart_in32(void __iomem *addr) |
| 40 | { |
| 41 | if (little_endian) |
| 42 | return in_le32(addr); |
| 43 | else |
| 44 | return in_be32(addr); |
| 45 | } |
| 46 | |
| 47 | static void uart_out32(void __iomem *addr, u32 val) |
| 48 | { |
| 49 | if (little_endian) |
| 50 | out_le32(addr, val); |
| 51 | else |
| 52 | out_be32(addr, val); |
| 53 | } |
| 54 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 55 | static int uartlite_serial_putc(struct udevice *dev, const char ch) |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 56 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 57 | struct uartlite_plat *plat = dev_get_plat(dev); |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 58 | struct uartlite *regs = plat->regs; |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 59 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 60 | if (uart_in32(®s->status) & SR_TX_FIFO_FULL) |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 61 | return -EAGAIN; |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 62 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 63 | uart_out32(®s->tx_fifo, ch & 0xff); |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 64 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 65 | return 0; |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 66 | } |
| 67 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 68 | static int uartlite_serial_getc(struct udevice *dev) |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 69 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 70 | struct uartlite_plat *plat = dev_get_plat(dev); |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 71 | struct uartlite *regs = plat->regs; |
| 72 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 73 | if (!(uart_in32(®s->status) & SR_RX_FIFO_VALID_DATA)) |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 74 | return -EAGAIN; |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 75 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 76 | return uart_in32(®s->rx_fifo) & 0xff; |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 79 | static int uartlite_serial_pending(struct udevice *dev, bool input) |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 80 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 81 | struct uartlite_plat *plat = dev_get_plat(dev); |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 82 | struct uartlite *regs = plat->regs; |
wdenk | 1249065 | 2004-04-18 21:13:41 +0000 | [diff] [blame] | 83 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 84 | if (input) |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 85 | return uart_in32(®s->status) & SR_RX_FIFO_VALID_DATA; |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 86 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 87 | return !(uart_in32(®s->status) & SR_TX_FIFO_EMPTY); |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 88 | } |
| 89 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 90 | static int uartlite_serial_probe(struct udevice *dev) |
Michal Simek | d40a252 | 2012-07-02 10:32:18 +0200 | [diff] [blame] | 91 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 92 | struct uartlite_plat *plat = dev_get_plat(dev); |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 93 | struct uartlite *regs = plat->regs; |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 94 | int ret; |
Michal Simek | e5b3c1d | 2014-01-21 07:29:47 +0100 | [diff] [blame] | 95 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 96 | uart_out32(®s->control, 0); |
| 97 | uart_out32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); |
| 98 | ret = uart_in32(®s->status); |
| 99 | /* Endianness detection */ |
| 100 | if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) { |
| 101 | little_endian = true; |
| 102 | uart_out32(®s->control, ULITE_CONTROL_RST_RX | |
| 103 | ULITE_CONTROL_RST_TX); |
| 104 | } |
Michal Simek | e5b3c1d | 2014-01-21 07:29:47 +0100 | [diff] [blame] | 105 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 106 | return 0; |
Michal Simek | d40a252 | 2012-07-02 10:32:18 +0200 | [diff] [blame] | 107 | } |
| 108 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 109 | static int uartlite_serial_of_to_plat(struct udevice *dev) |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 110 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 111 | struct uartlite_plat *plat = dev_get_plat(dev); |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 112 | |
Masahiro Yamada | 1096ae1 | 2020-07-17 14:36:46 +0900 | [diff] [blame] | 113 | plat->regs = dev_read_addr_ptr(dev); |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 114 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 115 | return 0; |
Marek Vasut | 5bcdf24 | 2012-09-09 18:48:28 +0200 | [diff] [blame] | 116 | } |
Michal Simek | 75348da | 2011-09-25 21:03:08 +0000 | [diff] [blame] | 117 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 118 | static const struct dm_serial_ops uartlite_serial_ops = { |
| 119 | .putc = uartlite_serial_putc, |
| 120 | .pending = uartlite_serial_pending, |
| 121 | .getc = uartlite_serial_getc, |
| 122 | }; |
Michal Simek | d40a252 | 2012-07-02 10:32:18 +0200 | [diff] [blame] | 123 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 124 | static const struct udevice_id uartlite_serial_ids[] = { |
| 125 | { .compatible = "xlnx,opb-uartlite-1.00.b", }, |
| 126 | { .compatible = "xlnx,xps-uartlite-1.00.a" }, |
| 127 | { } |
| 128 | }; |
Marek Vasut | d97fb5c | 2012-09-12 19:45:58 +0200 | [diff] [blame] | 129 | |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 130 | U_BOOT_DRIVER(serial_uartlite) = { |
| 131 | .name = "serial_uartlite", |
| 132 | .id = UCLASS_SERIAL, |
| 133 | .of_match = uartlite_serial_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 134 | .of_to_plat = uartlite_serial_of_to_plat, |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 135 | .plat_auto = sizeof(struct uartlite_plat), |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 136 | .probe = uartlite_serial_probe, |
| 137 | .ops = &uartlite_serial_ops, |
Michal Simek | 7e4372a | 2015-12-01 14:24:20 +0100 | [diff] [blame] | 138 | }; |
Michal Simek | 8af618b | 2015-12-14 16:55:10 +0100 | [diff] [blame] | 139 | |
| 140 | #ifdef CONFIG_DEBUG_UART_UARTLITE |
| 141 | |
| 142 | #include <debug_uart.h> |
| 143 | |
| 144 | static inline void _debug_uart_init(void) |
| 145 | { |
Pali Rohár | 8864b35 | 2022-05-27 22:15:24 +0200 | [diff] [blame] | 146 | struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE); |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 147 | int ret; |
Michal Simek | 8af618b | 2015-12-14 16:55:10 +0100 | [diff] [blame] | 148 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 149 | uart_out32(®s->control, 0); |
| 150 | uart_out32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); |
Ashok Reddy Soma | 5190dec | 2020-12-01 00:34:47 -0700 | [diff] [blame] | 151 | ret = uart_in32(®s->status); |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 152 | /* Endianness detection */ |
| 153 | if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) { |
| 154 | little_endian = true; |
| 155 | uart_out32(®s->control, ULITE_CONTROL_RST_RX | |
| 156 | ULITE_CONTROL_RST_TX); |
| 157 | } |
Michal Simek | 8af618b | 2015-12-14 16:55:10 +0100 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | static inline void _debug_uart_putc(int ch) |
| 161 | { |
Pali Rohár | 8864b35 | 2022-05-27 22:15:24 +0200 | [diff] [blame] | 162 | struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE); |
Michal Simek | 8af618b | 2015-12-14 16:55:10 +0100 | [diff] [blame] | 163 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 164 | while (uart_in32(®s->status) & SR_TX_FIFO_FULL) |
Michal Simek | 8af618b | 2015-12-14 16:55:10 +0100 | [diff] [blame] | 165 | ; |
| 166 | |
T Karthik Reddy | 070ffd2 | 2020-08-14 03:02:15 -0600 | [diff] [blame] | 167 | uart_out32(®s->tx_fifo, ch & 0xff); |
Michal Simek | 8af618b | 2015-12-14 16:55:10 +0100 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | DEBUG_UART_FUNCS |
| 171 | #endif |