| commit | e5b3c1d7c7c6f21fddfb4cafed1c0ff6be440a0c | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Tue Jan 21 07:29:47 2014 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Tue Feb 04 16:48:57 2014 +0100 |
| tree | 65a9ba250384539ce17006498974a2e38ad753ff | |
| parent | 65ffdc5acf56ed4c0aec2e2777b6063c105d2c5b [diff] |
serial: uartlite: Reset RX/TX in init Just to be sure that there is no pending data. Signed-off-by: Michal Simek <michal.simek@xilinx.com>