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git01.mediatek.com / filogic / uboot / d84f7833d50f3dc23d972d9f9d152c7225d3841b / . / arch / arm / include / asm / arch-am33xx / ddr_defs.h
blob: 388336f9d70a2aab663022acba58a5da30fc860c [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * ddr_defs.h
3 *
4 * ddr specific header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef _DDR_DEFS_H
20#define _DDR_DEFS_H
21
22#include <asm/arch/hardware.h>
23
24/* AM335X EMIF Register values */
25#define EMIF_SDMGT 0x80000000
26#define EMIF_SDRAM 0x00004650
27#define EMIF_PHYCFG 0x2
28#define DDR_PHY_RESET (0x1 << 10)
29#define DDR_FUNCTIONAL_MODE_EN 0x1
30#define DDR_PHY_READY (0x1 << 2)
31#define VTP_CTRL_READY (0x1 << 5)
32#define VTP_CTRL_ENABLE (0x1 << 6)
33#define VTP_CTRL_LOCK_EN (0x1 << 4)
34#define VTP_CTRL_START_EN (0x1)
35#define DDR2_RATIO 0x80
36#define CMD_FORCE 0x00
37#define CMD_DELAY 0x00
38
Chase Maupin2cf9ba82012-02-13 05:57:27 +0000[diff] [blame]39#define EMIF_READ_LATENCY 0x05
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]40#define EMIF_TIM1 0x0666B3D6
41#define EMIF_TIM2 0x143731DA
42#define EMIF_TIM3 0x00000347
43#define EMIF_SDCFG 0x43805332
44#define EMIF_SDREF 0x0000081a
45#define DDR2_DLL_LOCK_DIFF 0x0
46#define DDR2_RD_DQS 0x12
47#define DDR2_PHY_FIFO_WE 0x80
48
49#define DDR2_INVERT_CLKOUT 0x00
50#define DDR2_WR_DQS 0x00
51#define DDR2_PHY_WRLVL 0x00
52#define DDR2_PHY_GATELVL 0x00
53#define DDR2_PHY_WR_DATA 0x40
54#define PHY_RANK0_DELAY 0x01
55#define PHY_DLL_LOCK_DIFF 0x0
56#define DDR_IOCTRL_VALUE 0x18B
57
58/**
59 * This structure represents the EMIF registers on AM33XX devices.
60 */
61struct emif_regs {
62 unsigned int sdrrev; /* offset 0x00 */
63 unsigned int sdrstat; /* offset 0x04 */
64 unsigned int sdrcr; /* offset 0x08 */
65 unsigned int sdrcr2; /* offset 0x0C */
66 unsigned int sdrrcr; /* offset 0x10 */
67 unsigned int sdrrcsr; /* offset 0x14 */
68 unsigned int sdrtim1; /* offset 0x18 */
69 unsigned int sdrtim1sr; /* offset 0x1C */
70 unsigned int sdrtim2; /* offset 0x20 */
71 unsigned int sdrtim2sr; /* offset 0x24 */
72 unsigned int sdrtim3; /* offset 0x28 */
73 unsigned int sdrtim3sr; /* offset 0x2C */
74 unsigned int res1[2];
75 unsigned int sdrmcr; /* offset 0x38 */
76 unsigned int sdrmcsr; /* offset 0x3C */
77 unsigned int res2[8];
78 unsigned int sdritr; /* offset 0x60 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]79 unsigned int res3[32];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]80 unsigned int ddrphycr; /* offset 0xE4 */
81 unsigned int ddrphycsr; /* offset 0xE8 */
82 unsigned int ddrphycr2; /* offset 0xEC */
83};
84
85/**
86 * Encapsulates DDR PHY control and corresponding shadow registers.
87 */
88struct ddr_phy_control {
89 unsigned long reg;
90 unsigned long reg_sh;
91 unsigned long reg2;
92};
93
94/**
95 * Encapsulates SDRAM timing and corresponding shadow registers.
96 */
97struct sdram_timing {
98 unsigned long time1;
99 unsigned long time1_sh;
100 unsigned long time2;
101 unsigned long time2_sh;
102 unsigned long time3;
103 unsigned long time3_sh;
104};
105
106/**
107 * Encapsulates SDRAM configuration.
108 * (Includes refresh control registers) */
109struct sdram_config {
110 unsigned long sdrcr;
111 unsigned long sdrcr2;
112 unsigned long refresh;
113 unsigned long refresh_sh;
114};
115
116/**
117 * Configure SDRAM
118 */
119int config_sdram(struct sdram_config *cfg);
120
121/**
122 * Set SDRAM timings
123 */
124int set_sdram_timings(struct sdram_timing *val);
125
126/**
127 * Configure DDR PHY
128 */
129int config_ddr_phy(struct ddr_phy_control *cfg);
130
131/**
132 * This structure represents the DDR registers on AM33XX devices.
133 */
134struct ddr_regs {
135 unsigned int resv0[7];
136 unsigned int cm0csratio; /* offset 0x01C */
137 unsigned int cm0csforce; /* offset 0x020 */
138 unsigned int cm0csdelay; /* offset 0x024 */
139 unsigned int cm0dldiff; /* offset 0x028 */
140 unsigned int cm0iclkout; /* offset 0x02C */
141 unsigned int resv1[8];
142 unsigned int cm1csratio; /* offset 0x050 */
143 unsigned int cm1csforce; /* offset 0x054 */
144 unsigned int cm1csdelay; /* offset 0x058 */
145 unsigned int cm1dldiff; /* offset 0x05C */
146 unsigned int cm1iclkout; /* offset 0x060 */
147 unsigned int resv2[8];
148 unsigned int cm2csratio; /* offset 0x084 */
149 unsigned int cm2csforce; /* offset 0x088 */
150 unsigned int cm2csdelay; /* offset 0x08C */
151 unsigned int cm2dldiff; /* offset 0x090 */
152 unsigned int cm2iclkout; /* offset 0x094 */
153 unsigned int resv3[12];
154 unsigned int dt0rdsratio0; /* offset 0x0C8 */
155 unsigned int dt0rdsratio1; /* offset 0x0CC */
156 unsigned int resv4[3];
157 unsigned int dt0wdsratio0; /* offset 0x0DC */
158 unsigned int dt0wdsratio1; /* offset 0x0E0 */
159 unsigned int resv5[3];
160 unsigned int dt0wiratio0; /* offset 0x0F0 */
161 unsigned int dt0wiratio1; /* offset 0x0F4 */
162 unsigned int dt0giratio0; /* offset 0x0FC */
163 unsigned int dt0giratio1; /* offset 0x100 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]164 unsigned int resv6[1];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]165 unsigned int dt0fwsratio0; /* offset 0x108 */
166 unsigned int dt0fwsratio1; /* offset 0x10C */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]167 unsigned int resv7[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]168 unsigned int dt0wrsratio0; /* offset 0x120 */
169 unsigned int dt0wrsratio1; /* offset 0x124 */
170 unsigned int resv8[3];
171 unsigned int dt0rdelays0; /* offset 0x134 */
172 unsigned int dt0dldiff0; /* offset 0x138 */
173 unsigned int resv9[39];
174 unsigned int dt1rdelays0; /* offset 0x1D8 */
175};
176
177/**
178 * Encapsulates DDR CMD control registers.
179 */
180struct cmd_control {
181 unsigned long cmd0csratio;
182 unsigned long cmd0csforce;
183 unsigned long cmd0csdelay;
184 unsigned long cmd0dldiff;
185 unsigned long cmd0iclkout;
186 unsigned long cmd1csratio;
187 unsigned long cmd1csforce;
188 unsigned long cmd1csdelay;
189 unsigned long cmd1dldiff;
190 unsigned long cmd1iclkout;
191 unsigned long cmd2csratio;
192 unsigned long cmd2csforce;
193 unsigned long cmd2csdelay;
194 unsigned long cmd2dldiff;
195 unsigned long cmd2iclkout;
196};
197
198/**
199 * Encapsulates DDR DATA registers.
200 */
201struct ddr_data {
202 unsigned long datardsratio0;
203 unsigned long datardsratio1;
204 unsigned long datawdsratio0;
205 unsigned long datawdsratio1;
206 unsigned long datawiratio0;
207 unsigned long datawiratio1;
208 unsigned long datagiratio0;
209 unsigned long datagiratio1;
210 unsigned long datafwsratio0;
211 unsigned long datafwsratio1;
212 unsigned long datawrsratio0;
213 unsigned long datawrsratio1;
214 unsigned long datadldiff0;
215};
216
217/**
218 * Configure DDR CMD control registers
219 */
220int config_cmd_ctrl(struct cmd_control *cmd);
221
222/**
223 * Configure DDR DATA registers
224 */
225int config_ddr_data(int data_macrono, struct ddr_data *data);
226
227/**
228 * This structure represents the DDR io control on AM33XX devices.
229 */
230struct ddr_cmdtctrl {
231 unsigned int resv1[1];
232 unsigned int cm0ioctl;
233 unsigned int cm1ioctl;
234 unsigned int cm2ioctl;
235 unsigned int resv2[12];
236 unsigned int dt0ioctl;
237 unsigned int dt1ioctl;
238};
239
240/**
241 * Encapsulates DDR CMD & DATA io control registers.
242 */
243struct ddr_ioctrl {
244 unsigned long cmd1ctl;
245 unsigned long cmd2ctl;
246 unsigned long cmd3ctl;
247 unsigned long data1ctl;
248 unsigned long data2ctl;
249};
250
251/**
252 * Configure DDR io control registers
253 */
254int config_io_ctrl(struct ddr_ioctrl *ioctrl);
255
256struct ddr_ctrl {
257 unsigned int ddrioctrl;
258 unsigned int resv1[325];
259 unsigned int ddrckectrl;
260};
261
262void config_ddr(void);
263
264#endif /* _DDR_DEFS_H */