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git01.mediatek.com / filogic / uboot / d79de1d950d4779583a97be8eaab135d2bca3565 / . / board / ms7722se / lowlevel_init.S
blob: db859f48ad240a708740edab70ee8e6a2c5cb7b4 [file] [log] [blame]
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]1/*
2 * Copyright (C) 2007
3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Wolfgang Denk0a5c2142007-12-27 01:52:50 +0100[diff] [blame]4 *
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]5 * Copyright (C) 2007
6 * Kenati Technologies, Inc.
7 *
8 * board/ms7722se/lowlevel_init.S
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame^]10 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]11 */
12
13#include <config.h>
14#include <version.h>
15
16#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]17#include <asm/macro.h>
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]18
19/*
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]20 * Board specific low level init code, called _very_ early in the
21 * startup sequence. Relocation to SDRAM has not happened yet, no
22 * stack is available, bss section has not been initialised, etc.
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]23 *
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]24 * (Note: As no stack is available, no subroutines can be called...).
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]25 */
26
27 .global lowlevel_init
28
29 .text
30 .align 2
31
32lowlevel_init:
33
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]34 /*
35 * Cache Control Register
36 * Instruction Cache Invalidate
37 */
38 write32 CCR_A, CCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]39
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]40 /*
41 * Address of MMU Control Register
42 * TI == TLB Invalidate bit
43 */
44 write32 MMUCR_A, MMUCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]45
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]46 /* Address of Power Control Register 0 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]47 write32 MSTPCR0_A, MSTPCR0_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]48
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]49 /* Address of Power Control Register 2 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]50 write32 MSTPCR2_A, MSTPCR2_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]51
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]52 write16 SBSCR_A, SBSCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]53
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]54 write16 PSCR_A, PSCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]55
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]56 /* 0xA4520004 (Watchdog Control / Status Register) */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]57! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]58
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]59 /* 0xA4520000 (Watchdog Count Register) */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]60 write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]61
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]62 /* 0xA4520004 (Watchdog Control / Status Register) */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]63 write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]64
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]65 /* 0xA4150000 Frequency control register */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]66 write32 FRQCR_A, FRQCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]67
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]68 write32 CCR_A, CCR_D_2
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]69
70bsc_init:
71
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]72 write16 PSELA_A, PSELA_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]73
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]74 write16 DRVCR_A, DRVCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]75
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]76 write16 PCCR_A, PCCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]77
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]78 write16 PECR_A, PECR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]79
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]80 write16 PJCR_A, PJCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]81
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]82 write16 PXCR_A, PXCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]83
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]84 write32 CMNCR_A, CMNCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]85
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]86 write32 CS0BCR_A, CS0BCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]87
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]88 write32 CS2BCR_A, CS2BCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]89
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]90 write32 CS4BCR_A, CS4BCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]91
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]92 write32 CS5ABCR_A, CS5ABCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]93
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]94 write32 CS5BBCR_A, CS5BBCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]95
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]96 write32 CS6ABCR_A, CS6ABCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]97
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]98 write32 CS0WCR_A, CS0WCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]99
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]100 write32 CS2WCR_A, CS2WCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]101
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]102 write32 CS4WCR_A, CS4WCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]103
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]104 write32 CS5AWCR_A, CS5AWCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]105
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]106 write32 CS5BWCR_A, CS5BWCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]107
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]108 write32 CS6AWCR_A, CS6AWCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]109
110 ! SDRAM initialization
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]111 write32 SDCR_A, SDCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]112
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]113 write32 SDWCR_A, SDWCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]114
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]115 write32 SDPCR_A, SDPCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]116
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]117 write32 RTCOR_A, RTCOR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]118
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]119 write32 RTCSR_A, RTCSR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]120
Nobuhiro Iwamatsufcbff802009-01-11 17:48:56 +0900[diff] [blame]121 write8 SDMR3_A, SDMR3_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]122
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]123 ! BL bit off (init = ON) (?!?)
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]124
125 stc sr, r0 ! BL bit off(init=ON)
126 mov.l SR_MASK_D, r1
127 and r1, r0
128 ldc r0, sr
129
130 rts
131 mov #0, r0
132
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]133 .align 2
134
Wolfgang Denk0a5c2142007-12-27 01:52:50 +0100[diff] [blame]135CCR_A: .long CCR
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]136MMUCR_A: .long MMUCR
137MSTPCR0_A: .long MSTPCR0
138MSTPCR2_A: .long MSTPCR2
139SBSCR_A: .long SBSCR
140PSCR_A: .long PSCR
141RWTCSR_A: .long RWTCSR
142RWTCNT_A: .long RWTCNT
143FRQCR_A: .long FRQCR
144
145CCR_D: .long 0x00000800
146CCR_D_2: .long 0x00000103
147MMUCR_D: .long 0x00000004
148MSTPCR0_D: .long 0x00001001
149MSTPCR2_D: .long 0xffffffff
150FRQCR_D: .long 0x07022538
151
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]152PSELA_A: .long 0xa405014E
153PSELA_D: .word 0x0A10
Wolfgang Denk0a5c2142007-12-27 01:52:50 +0100[diff] [blame]154 .align 2
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]155
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]156DRVCR_A: .long 0xa405018A
157DRVCR_D: .word 0x0554
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]158 .align 2
159
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]160PCCR_A: .long 0xa4050104
161PCCR_D: .word 0x8800
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]162 .align 2
163
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]164PECR_A: .long 0xa4050108
165PECR_D: .word 0x0000
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]166 .align 2
167
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]168PJCR_A: .long 0xa4050110
169PJCR_D: .word 0x1000
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]170 .align 2
171
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]172PXCR_A: .long 0xa4050148
173PXCR_D: .word 0x0AAA
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]174 .align 2
175
176CMNCR_A: .long CMNCR
177CMNCR_D: .long 0x00000013
178CS0BCR_A: .long CS0BCR ! Flash bank 1
179CS0BCR_D: .long 0x24920400
180CS2BCR_A: .long CS2BCR ! SRAM
181CS2BCR_D: .long 0x24920400
182CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
183CS4BCR_D: .long 0x24920400
184CS5ABCR_A: .long CS5ABCR ! Ext slot
185CS5ABCR_D: .long 0x24920400
186CS5BBCR_A: .long CS5BBCR ! USB controller
187CS5BBCR_D: .long 0x24920400
188CS6ABCR_A: .long CS6ABCR ! Ethernet
189CS6ABCR_D: .long 0x24920400
190
191CS0WCR_A: .long CS0WCR
192CS0WCR_D: .long 0x00000300
193CS2WCR_A: .long CS2WCR
194CS2WCR_D: .long 0x00000300
195CS4WCR_A: .long CS4WCR
196CS4WCR_D: .long 0x00000300
197CS5AWCR_A: .long CS5AWCR
198CS5AWCR_D: .long 0x00000300
199CS5BWCR_A: .long CS5BWCR
200CS5BWCR_D: .long 0x00000300
201CS6AWCR_A: .long CS6AWCR
202CS6AWCR_D: .long 0x00000300
203
204SDCR_A: .long SBSC_SDCR
205SDCR_D: .long 0x00020809
206SDWCR_A: .long SBSC_SDWCR
207SDWCR_D: .long 0x00164d0d
208SDPCR_A: .long SBSC_SDPCR
209SDPCR_D: .long 0x00000087
210RTCOR_A: .long SBSC_RTCOR
211RTCOR_D: .long 0xA55A0034
212RTCSR_A: .long SBSC_RTCSR
213RTCSR_D: .long 0xA55A0010
214SDMR3_A: .long 0xFE500180
Nobuhiro Iwamatsufcbff802009-01-11 17:48:56 +0900[diff] [blame]215SDMR3_D: .long 0x0
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]216
217 .align 1
218
219SBSCR_D: .word 0x0040
220PSCR_D: .word 0x0000
221RWTCSR_D_1: .word 0xA507
222RWTCSR_D_2: .word 0xA507
223RWTCNT_D: .word 0x5A00
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]224 .align 2
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]225
226SR_MASK_D: .long 0xEFFFFF0F