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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hueee86ff2015-10-26 19:47:52 +08002/*
3 * Copyright (C) 2015 Freescale Semiconductor
Yangbo Lubb32e682021-06-03 10:51:19 +08004 * Copyright 2019-2021 NXP
Mingkai Hueee86ff2015-10-26 19:47:52 +08005 */
6
7#ifndef __LS1043A_COMMON_H
8#define __LS1043A_COMMON_H
9
Sumit Garg2a2857b2017-03-30 09:52:38 +053010/* SPL build */
11#ifdef CONFIG_SPL_BUILD
12#define SPL_NO_FMAN
13#define SPL_NO_DSPI
14#define SPL_NO_PCIE
15#define SPL_NO_ENV
16#define SPL_NO_MISC
17#define SPL_NO_USB
18#define SPL_NO_SATA
19#define SPL_NO_QE
20#define SPL_NO_EEPROM
21#endif
22#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
23#define SPL_NO_MMC
24#endif
Yangbo Lu83c4ece2017-09-15 09:51:58 +080025#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
Sumit Garg2a2857b2017-03-30 09:52:38 +053026#define SPL_NO_IFC
27#endif
28
Mingkai Hueee86ff2015-10-26 19:47:52 +080029#define CONFIG_REMAKE_ELF
Mingkai Hueee86ff2015-10-26 19:47:52 +080030
Bharat Bhushan882b6322017-03-22 12:06:27 +053031#include <asm/arch/stream_id_lsch2.h>
Mingkai Hueee86ff2015-10-26 19:47:52 +080032#include <asm/arch/config.h>
Mingkai Hueee86ff2015-10-26 19:47:52 +080033
34/* Link Definitions */
Rajesh Bhagatb89aed42018-11-05 18:02:44 +000035#ifdef CONFIG_TFABOOT
36#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
37#else
Mingkai Hueee86ff2015-10-26 19:47:52 +080038#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
Rajesh Bhagatb89aed42018-11-05 18:02:44 +000039#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +080040
Mingkai Hueee86ff2015-10-26 19:47:52 +080041#define CONFIG_VERY_BIG_RAM
42#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
43#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
44#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shaohui Xief6c83952015-11-23 15:23:48 +080045#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
Mingkai Hueee86ff2015-10-26 19:47:52 +080046
Michael Wallef056e0f2020-06-01 21:53:26 +020047#define CPU_RELEASE_ADDR secondary_boot_addr
Hou Zhiqiangc7098fa2015-10-26 19:47:57 +080048
Mingkai Hueee86ff2015-10-26 19:47:52 +080049/* Generic Timer Definitions */
50#define COUNTER_FREQUENCY 25000000 /* 25MHz */
51
Mingkai Hueee86ff2015-10-26 19:47:52 +080052/* Serial Port */
Mingkai Hueee86ff2015-10-26 19:47:52 +080053#define CONFIG_SYS_NS16550_SERIAL
54#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +080055#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Hueee86ff2015-10-26 19:47:52 +080056
Gong Qianyuf671f6c2015-10-26 19:47:56 +080057/* SD boot SPL */
58#ifdef CONFIG_SD_BOOT
Gong Qianyuf671f6c2015-10-26 19:47:56 +080059
Ruchika Guptad6b89202017-04-17 18:07:17 +053060#define CONFIG_SPL_MAX_SIZE 0x17000
Gong Qianyuf671f6c2015-10-26 19:47:56 +080061#define CONFIG_SPL_STACK 0x1001e000
62#define CONFIG_SPL_PAD_TO 0x1d000
63
York Sunf7eed6b2017-09-28 08:42:16 -070064#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
65 CONFIG_SPL_BSS_MAX_SIZE)
Gong Qianyuf671f6c2015-10-26 19:47:56 +080066#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
York Sunf7eed6b2017-09-28 08:42:16 -070067#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
Gong Qianyuf671f6c2015-10-26 19:47:56 +080068#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Ruchika Guptad6b89202017-04-17 18:07:17 +053069
Udit Agarwal22ec2382019-11-07 16:11:32 +000070#ifdef CONFIG_NXP_ESBC
Ruchika Guptad6b89202017-04-17 18:07:17 +053071#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
72/*
73 * HDR would be appended at end of image and copied to DDR along
74 * with U-Boot image. Here u-boot max. size is 512K. So if binary
75 * size increases then increase this size in case of secure boot as
76 * it uses raw u-boot image instead of fit image.
77 */
78#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
79#else
80#define CONFIG_SYS_MONITOR_LEN 0x100000
Udit Agarwal22ec2382019-11-07 16:11:32 +000081#endif /* ifdef CONFIG_NXP_ESBC */
Gong Qianyuf671f6c2015-10-26 19:47:56 +080082#endif
83
Gong Qianyu8168a0f2015-10-26 19:47:53 +080084/* NAND SPL */
85#ifdef CONFIG_NAND_BOOT
86#define CONFIG_SPL_PBL_PAD
Gong Qianyu8168a0f2015-10-26 19:47:53 +080087#define CONFIG_SPL_MAX_SIZE 0x1a000
88#define CONFIG_SPL_STACK 0x1001d000
89#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
90#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
91#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
92#define CONFIG_SPL_BSS_START_ADDR 0x80100000
93#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
94#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Ruchika Guptaba688752017-04-17 18:07:18 +053095
Udit Agarwal22ec2382019-11-07 16:11:32 +000096#ifdef CONFIG_NXP_ESBC
Ruchika Guptaba688752017-04-17 18:07:18 +053097#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Udit Agarwal22ec2382019-11-07 16:11:32 +000098#endif /* ifdef CONFIG_NXP_ESBC */
Ruchika Guptaba688752017-04-17 18:07:18 +053099
100#ifdef CONFIG_U_BOOT_HDR_SIZE
101/*
102 * HDR would be appended at end of image and copied to DDR along
103 * with U-Boot image. Here u-boot max. size is 512K. So if binary
104 * size increases then increase this size in case of secure boot as
105 * it uses raw u-boot image instead of fit image.
106 */
107#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
108#else
109#define CONFIG_SYS_MONITOR_LEN 0x100000
110#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
111
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800112#endif
113
Biwen Li46de4002021-02-05 19:01:56 +0800114/* GPIO */
Biwen Li46de4002021-02-05 19:01:56 +0800115
Mingkai Hueee86ff2015-10-26 19:47:52 +0800116/* IFC */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530117#ifndef SPL_NO_IFC
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000118#if defined(CONFIG_TFABOOT) || \
119 (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
Mingkai Hueee86ff2015-10-26 19:47:52 +0800120/*
121 * CONFIG_SYS_FLASH_BASE has the final address (core view)
122 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
123 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
124 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
125 */
126#define CONFIG_SYS_FLASH_BASE 0x60000000
127#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
128#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
129
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900130#ifdef CONFIG_MTD_NOR_FLASH
Mingkai Hueee86ff2015-10-26 19:47:52 +0800131#define CONFIG_SYS_FLASH_QUIET_TEST
132#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
133#endif
Gong Qianyu760df892016-01-25 15:16:06 +0800134#endif
Sumit Garg2a2857b2017-03-30 09:52:38 +0530135#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +0800136
137/* I2C */
Mingkai Hueee86ff2015-10-26 19:47:52 +0800138
139/* PCIe */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530140#ifndef SPL_NO_PCIE
Mingkai Hueee86ff2015-10-26 19:47:52 +0800141#define CONFIG_PCIE1 /* PCIE controller 1 */
142#define CONFIG_PCIE2 /* PCIE controller 2 */
143#define CONFIG_PCIE3 /* PCIE controller 3 */
Mingkai Hueee86ff2015-10-26 19:47:52 +0800144
Mingkai Hueee86ff2015-10-26 19:47:52 +0800145#ifdef CONFIG_PCI
Mingkai Hueee86ff2015-10-26 19:47:52 +0800146#define CONFIG_PCI_SCAN_SHOW
Mingkai Hueee86ff2015-10-26 19:47:52 +0800147#endif
Sumit Garg2a2857b2017-03-30 09:52:38 +0530148#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +0800149
Gong Qianyu51c18dc2016-01-25 15:16:05 +0800150/* DSPI */
Gong Qianyu51c18dc2016-01-25 15:16:05 +0800151
Shaohui Xie04643262015-10-26 19:47:54 +0800152/* FMan ucode */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530153#ifndef SPL_NO_FMAN
Shaohui Xie04643262015-10-26 19:47:54 +0800154#define CONFIG_SYS_DPAA_FMAN
155#ifdef CONFIG_SYS_DPAA_FMAN
156#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
157
Shaohui Xie04643262015-10-26 19:47:54 +0800158#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
159#endif
Sumit Garg2a2857b2017-03-30 09:52:38 +0530160#endif
Shaohui Xie04643262015-10-26 19:47:54 +0800161
Mingkai Hueee86ff2015-10-26 19:47:52 +0800162/* Miscellaneous configurable options */
Mingkai Hueee86ff2015-10-26 19:47:52 +0800163
164#define CONFIG_HWCONFIG
165#define HWCONFIG_BUFFER_SIZE 128
166
Sumit Garg2a2857b2017-03-30 09:52:38 +0530167#ifndef SPL_NO_MISC
Shengzhou Liu9d662542017-06-08 15:59:48 +0800168#ifndef CONFIG_SPL_BUILD
169#define BOOT_TARGET_DEVICES(func) \
170 func(MMC, mmc, 0) \
Mian Yousaf Kaukab6519df72019-01-29 16:38:40 +0100171 func(USB, usb, 0) \
172 func(DHCP, dhcp, na)
Shengzhou Liu9d662542017-06-08 15:59:48 +0800173#include <config_distro_bootcmd.h>
174#endif
175
Mingkai Hueee86ff2015-10-26 19:47:52 +0800176/* Initial environment variables */
177#define CONFIG_EXTRA_ENV_SETTINGS \
178 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Hueee86ff2015-10-26 19:47:52 +0800179 "fdt_high=0xffffffffffffffff\0" \
180 "initrd_high=0xffffffffffffffff\0" \
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200181 "fdt_addr=0x64f00000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530182 "kernel_addr=0x61000000\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800183 "scriptaddr=0x80000000\0" \
Sumit Garg9cbcc4d2017-06-05 23:51:51 +0530184 "scripthdraddr=0x80080000\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800185 "fdtheader_addr_r=0x80100000\0" \
186 "kernelheader_addr_r=0x80200000\0" \
187 "kernel_addr_r=0x81000000\0" \
Wen He335b3862018-11-20 16:55:25 +0800188 "kernel_start=0x1000000\0" \
189 "kernelheader_start=0x800000\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800190 "fdt_addr_r=0x90000000\0" \
191 "load_addr=0xa0000000\0" \
Manish Tomar8d388012020-11-05 14:08:55 +0530192 "kernelheader_addr=0x60600000\0" \
Qianyu Gong2758edf2016-03-15 16:35:57 +0800193 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530194 "kernelheader_size=0x40000\0" \
Shengzhou Liu42862752017-11-09 17:57:55 +0800195 "kernel_addr_sd=0x8000\0" \
196 "kernel_size_sd=0x14000\0" \
Manish Tomar8d388012020-11-05 14:08:55 +0530197 "kernelhdr_addr_sd=0x3000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530198 "kernelhdr_size_sd=0x10\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800199 "console=ttyS0,115200\0" \
York Sunf7eed6b2017-09-28 08:42:16 -0700200 "boot_os=y\0" \
Tom Rini5ad8e112017-10-22 17:55:07 -0400201 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800202 BOOTENV \
203 "boot_scripts=ls1043ardb_boot.scr\0" \
Sumit Garg9cbcc4d2017-06-05 23:51:51 +0530204 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800205 "scan_dev_for_boot_part=" \
206 "part list ${devtype} ${devnum} devplist; " \
207 "env exists devplist || setenv devplist 1; " \
208 "for distro_bootpart in ${devplist}; do " \
209 "if fstype ${devtype} " \
210 "${devnum}:${distro_bootpart} " \
211 "bootfstype; then " \
212 "run scan_dev_for_boot; " \
213 "fi; " \
214 "done\0" \
Sumit Garg9cbcc4d2017-06-05 23:51:51 +0530215 "boot_a_script=" \
216 "load ${devtype} ${devnum}:${distro_bootpart} " \
217 "${scriptaddr} ${prefix}${script}; " \
218 "env exists secureboot && load ${devtype} " \
219 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai25355ec2019-04-23 05:52:17 +0000220 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
221 "env exists secureboot " \
Sumit Garg9cbcc4d2017-06-05 23:51:51 +0530222 "&& esbc_validate ${scripthdraddr};" \
223 "source ${scriptaddr}\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800224 "qspi_bootcmd=echo Trying load from qspi..;" \
225 "sf probe && sf read $load_addr " \
Wen Hecabe55c2019-11-14 15:08:15 +0800226 "$kernel_start $kernel_size; env exists secureboot " \
227 "&& sf read $kernelheader_addr_r $kernelheader_start " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530228 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
229 "bootm $load_addr#$board\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800230 "nor_bootcmd=echo Trying load from nor..;" \
231 "cp.b $kernel_addr $load_addr " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530232 "$kernel_size; env exists secureboot " \
233 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
234 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
235 "bootm $load_addr#$board\0" \
Wen He335b3862018-11-20 16:55:25 +0800236 "nand_bootcmd=echo Trying load from NAND..;" \
237 "nand info; nand read $load_addr " \
238 "$kernel_start $kernel_size; env exists secureboot " \
239 "&& nand read $kernelheader_addr_r $kernelheader_start " \
240 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
241 "bootm $load_addr#$board\0" \
Shengzhou Liu42862752017-11-09 17:57:55 +0800242 "sd_bootcmd=echo Trying load from SD ..;" \
243 "mmcinfo; mmc read $load_addr " \
244 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530245 "env exists secureboot && mmc read $kernelheader_addr_r " \
246 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
247 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu42862752017-11-09 17:57:55 +0800248 "bootm $load_addr#$board\0"
249
Wenbin Song1738ca72016-07-21 18:55:16 +0800250
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000251#ifdef CONFIG_TFABOOT
252#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
253 "env exists secureboot && esbc_halt;"
254#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
255 "env exists secureboot && esbc_halt;"
256#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
257 "env exists secureboot && esbc_halt;"
Pankit Garg69210722018-12-27 04:37:53 +0000258#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
259 "env exists secureboot && esbc_halt;"
Sumit Garg2a2857b2017-03-30 09:52:38 +0530260#endif
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000261#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +0800262
263/* Monitor Command Prompt */
264#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530265
Mingkai Hueee86ff2015-10-26 19:47:52 +0800266#define CONFIG_SYS_MAXARGS 64 /* max command args */
267
268#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
269
Simon Glass89e0a3a2017-05-17 08:23:10 -0600270#include <asm/arch/soc.h>
271
Mingkai Hueee86ff2015-10-26 19:47:52 +0800272#endif /* __LS1043A_COMMON_H */