blob: 23b9969f84b89c012e872f33cf3f6663e3200495 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +00002/*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Biwen Li6a2d8d12020-05-01 20:04:13 +08004 * Copyright 2020 NXP
Poonam Aggrwala2ec1352011-02-09 19:17:53 +00005 */
6
7/*
8 * P010 RDB board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Simon Glassfb64e362020-05-10 11:40:09 -060014#include <linux/stringify.h>
15
Prabhakar Kushwahad324f472013-04-16 13:27:44 +053016#include <asm/config_mpc85xx.h>
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000017
18#ifdef CONFIG_SDCARD
Ying Zhang1233cbc2014-01-24 15:50:09 +080019#define CONFIG_SPL_FLUSH_IMAGE
20#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang1233cbc2014-01-24 15:50:09 +080021#define CONFIG_SPL_PAD_TO 0x18000
22#define CONFIG_SPL_MAX_SIZE (96 * 1024)
23#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
24#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
25#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
26#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
27#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Ying Zhang1233cbc2014-01-24 15:50:09 +080028#ifdef CONFIG_SPL_BUILD
29#define CONFIG_SPL_COMMON_INIT_DDR
30#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000031#endif
32
33#ifdef CONFIG_SPIFLASH
Udit Agarwald2dd2f72019-11-07 16:11:39 +000034#ifdef CONFIG_NXP_ESBC
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000035#define CONFIG_RAMBOOT_SPIFLASH
Ruchika Gupta604a9592014-09-29 11:14:35 +053036#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ying Zhang1233cbc2014-01-24 15:50:09 +080037#else
Ying Zhang1233cbc2014-01-24 15:50:09 +080038#define CONFIG_SPL_SPI_FLASH_MINIMAL
39#define CONFIG_SPL_FLUSH_IMAGE
40#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang1233cbc2014-01-24 15:50:09 +080041#define CONFIG_SPL_PAD_TO 0x18000
42#define CONFIG_SPL_MAX_SIZE (96 * 1024)
43#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
44#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
45#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
46#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
47#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Ying Zhang1233cbc2014-01-24 15:50:09 +080048#ifdef CONFIG_SPL_BUILD
49#define CONFIG_SPL_COMMON_INIT_DDR
50#endif
51#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000052#endif
53
Miquel Raynald0935362019-10-03 19:50:03 +020054#ifdef CONFIG_MTD_RAW_NAND
Udit Agarwald2dd2f72019-11-07 16:11:39 +000055#ifdef CONFIG_NXP_ESBC
Prabhakar Kushwaha66d6aa82013-04-16 13:28:12 +053056#define CONFIG_SPL_INIT_MINIMAL
Prabhakar Kushwaha66d6aa82013-04-16 13:28:12 +053057#define CONFIG_SPL_FLUSH_IMAGE
58#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
59
Prabhakar Kushwaha66d6aa82013-04-16 13:28:12 +053060#define CONFIG_SPL_MAX_SIZE 8192
61#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
62#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053063#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwaha66d6aa82013-04-16 13:28:12 +053064#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
65#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
Ying Zhang1233cbc2014-01-24 15:50:09 +080066#else
Ying Zhang1233cbc2014-01-24 15:50:09 +080067#ifdef CONFIG_TPL_BUILD
Ying Zhang1233cbc2014-01-24 15:50:09 +080068#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhang1233cbc2014-01-24 15:50:09 +080069#define CONFIG_SPL_NAND_INIT
Ying Zhang1233cbc2014-01-24 15:50:09 +080070#define CONFIG_SPL_COMMON_INIT_DDR
71#define CONFIG_SPL_MAX_SIZE (128 << 10)
Ying Zhang1233cbc2014-01-24 15:50:09 +080072#define CONFIG_SYS_MPC85XX_NO_RESETVEC
73#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
74#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
75#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
Ying Zhang1233cbc2014-01-24 15:50:09 +080076#elif defined(CONFIG_SPL_BUILD)
77#define CONFIG_SPL_INIT_MINIMAL
Ying Zhang1233cbc2014-01-24 15:50:09 +080078#define CONFIG_SPL_NAND_MINIMAL
79#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhang1233cbc2014-01-24 15:50:09 +080080#define CONFIG_SPL_MAX_SIZE 8192
81#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
82#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
83#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
Dipen Dudhat2f143ed2011-07-28 14:47:28 -050084#endif
Ying Zhang1233cbc2014-01-24 15:50:09 +080085#define CONFIG_SPL_PAD_TO 0x20000
86#define CONFIG_TPL_PAD_TO 0x20000
87#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang1233cbc2014-01-24 15:50:09 +080088#endif
89#endif
Ruchika Guptab36ccc52011-06-08 22:52:48 -050090
91#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
92#define CONFIG_RAMBOOT_NAND
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053093#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ruchika Guptab36ccc52011-06-08 22:52:48 -050094#endif
95
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000096#ifndef CONFIG_RESET_VECTOR_ADDRESS
97#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
98#endif
99
Tom Rini0a01a442019-01-22 17:09:24 -0500100#ifdef CONFIG_TPL_BUILD
Tom Rini15cd5be2021-12-14 13:36:33 -0500101#define CONFIG_SYS_MONITOR_BASE 0xD0001000
Tom Rini0a01a442019-01-22 17:09:24 -0500102#elif defined(CONFIG_SPL_BUILD)
Prabhakar Kushwaha66d6aa82013-04-16 13:28:12 +0530103#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
104#else
105#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000106#endif
107
108/* High Level Configuration Options */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000109
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000110#if defined(CONFIG_PCI)
Robert P. J. Daya8099812016-05-03 19:52:49 -0400111#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
112#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000113
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000114/*
115 * PCI Windows
116 * Memory space is mapped 1-1, but I/O space must start from 0.
117 */
118/* controller 1, Slot 1, tgtid 1, Base address a000 */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000119#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
120#ifdef CONFIG_PHYS_64BIT
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000121#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
122#else
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000123#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
124#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000125#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000126#ifdef CONFIG_PHYS_64BIT
127#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
128#else
129#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
130#endif
131
132/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Hou Zhiqiangd3cb8812020-05-01 19:06:28 +0800133#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
134#ifdef CONFIG_PHYS_64BIT
135#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
136#else
137#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
138#endif
139#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
140#ifdef CONFIG_PHYS_64BIT
141#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
142#else
143#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
144#endif
145
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000146#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000147#endif
148
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000149#define CONFIG_HWCONFIG
150/*
151 * These can be toggled for performance analysis, otherwise use default.
152 */
153#define CONFIG_L2_CACHE /* toggle L2 cache */
154#define CONFIG_BTB /* toggle branch predition */
155
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000156
157#define CONFIG_ENABLE_36BIT_PHYS
158
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000159/* DDR Setup */
York Sun66f05142012-02-29 12:36:51 +0000160#define CONFIG_SYS_DDR_RAW_TIMING
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000161#define CONFIG_SYS_SPD_BUS_NUM 1
162#define SPD_EEPROM_ADDRESS 0x52
163
164#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
165
166#ifndef __ASSEMBLY__
167extern unsigned long get_sdram_size(void);
168#endif
169#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
170#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
171#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
172
173#define CONFIG_DIMM_SLOTS_PER_CTLR 1
174#define CONFIG_CHIP_SELECTS_PER_CTRL 1
175
176/* DDR3 Controller Settings */
177#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
178#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
179#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
180#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
181#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
182#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
183#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000184#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
185#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
186#define CONFIG_SYS_DDR_RCW_1 0x00000000
187#define CONFIG_SYS_DDR_RCW_2 0x00000000
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800188#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
189#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000190#define CONFIG_SYS_DDR_TIMING_4 0x00000001
191#define CONFIG_SYS_DDR_TIMING_5 0x03402400
192
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800193#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
194#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
195#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000196#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
197#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800198#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
199#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000200#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800201#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000202
203/* settings for DDR3 at 667MT/s */
204#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
205#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
206#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
207#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
208#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
209#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
210#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
211#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
212#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
213
214#define CONFIG_SYS_CCSRBAR 0xffe00000
215#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
216
Dipen Dudhat2f143ed2011-07-28 14:47:28 -0500217/* Don't relocate CCSRBAR while in NAND_SPL */
Prabhakar Kushwaha66d6aa82013-04-16 13:28:12 +0530218#ifdef CONFIG_SPL_BUILD
Dipen Dudhat2f143ed2011-07-28 14:47:28 -0500219#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
220#endif
221
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000222/*
223 * Memory map
224 *
225 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
226 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
227 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
228 *
229 * Localbus non-cacheable
230 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
231 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
232 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
233 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
234 */
235
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000236/*
237 * IFC Definitions
238 */
239/* NOR Flash on IFC */
Prabhakar Kushwaha66d6aa82013-04-16 13:28:12 +0530240
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000241#define CONFIG_SYS_FLASH_BASE 0xee000000
242#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
243
244#ifdef CONFIG_PHYS_64BIT
245#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
246#else
247#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
248#endif
249
250#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
251 CSPR_PORT_SIZE_16 | \
252 CSPR_MSEL_NOR | \
253 CSPR_V)
254#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
255#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
256/* NOR Flash Timing Params */
257#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
258 FTIM0_NOR_TEADC(0x5) | \
259 FTIM0_NOR_TEAHC(0x5)
260#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
261 FTIM1_NOR_TRAD_NOR(0x0f)
262#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
263 FTIM2_NOR_TCH(0x4) | \
264 FTIM2_NOR_TWP(0x1c)
265#define CONFIG_SYS_NOR_FTIM3 0x0
266
267#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
268#define CONFIG_SYS_FLASH_QUIET_TEST
269#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000270
271#undef CONFIG_SYS_FLASH_CHECKSUM
272#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
273#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
274
275/* CFI for NOR Flash */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000276#define CONFIG_SYS_FLASH_EMPTY_INFO
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000277
278/* NAND Flash on IFC */
279#define CONFIG_SYS_NAND_BASE 0xff800000
280#ifdef CONFIG_PHYS_64BIT
281#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
282#else
283#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
284#endif
285
Zhao Qiangc655ef12013-09-26 09:10:32 +0800286#define CONFIG_MTD_PARTITION
Zhao Qiangc655ef12013-09-26 09:10:32 +0800287
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000288#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
289 | CSPR_PORT_SIZE_8 \
290 | CSPR_MSEL_NAND \
291 | CSPR_V)
292#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800293
York Sun7f945ca2016-11-16 13:30:06 -0800294#if defined(CONFIG_TARGET_P1010RDB_PA)
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000295#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
296 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
297 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
298 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
299 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
300 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
301 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800302
York Sun7f945ca2016-11-16 13:30:06 -0800303#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800304#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
305 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
306 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
307 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
308 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
309 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
310 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800311#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000312
Dipen Dudhat2f143ed2011-07-28 14:47:28 -0500313#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
314#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dipen Dudhat2f143ed2011-07-28 14:47:28 -0500315
York Sun7f945ca2016-11-16 13:30:06 -0800316#if defined(CONFIG_TARGET_P1010RDB_PA)
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000317/* NAND Flash Timing Params */
318#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
319 FTIM0_NAND_TWP(0x0C) | \
320 FTIM0_NAND_TWCHT(0x04) | \
321 FTIM0_NAND_TWH(0x05)
322#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
323 FTIM1_NAND_TWBE(0x1d) | \
324 FTIM1_NAND_TRR(0x07) | \
325 FTIM1_NAND_TRP(0x0c)
326#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
327 FTIM2_NAND_TREH(0x05) | \
328 FTIM2_NAND_TWHRE(0x0f)
329#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
330
York Sun7f945ca2016-11-16 13:30:06 -0800331#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800332/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
333/* ONFI NAND Flash mode0 Timing Params */
334#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
335 FTIM0_NAND_TWP(0x18) | \
336 FTIM0_NAND_TWCHT(0x07) | \
337 FTIM0_NAND_TWH(0x0a))
338#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
339 FTIM1_NAND_TWBE(0x39) | \
340 FTIM1_NAND_TRR(0x0e) | \
341 FTIM1_NAND_TRP(0x18))
342#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
343 FTIM2_NAND_TREH(0x0a) | \
344 FTIM2_NAND_TWHRE(0x1e))
345#define CONFIG_SYS_NAND_FTIM3 0x0
346#endif
347
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000348#define CONFIG_SYS_NAND_DDR_LAW 11
349
350/* Set up IFC registers for boot location NOR/NAND */
Miquel Raynald0935362019-10-03 19:50:03 +0200351#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
Dipen Dudhat2f143ed2011-07-28 14:47:28 -0500352#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
353#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
354#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
355#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
356#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
357#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
358#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
359#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
360#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
361#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
362#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
363#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
364#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
365#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
366#else
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000367#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
368#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
369#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
370#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
371#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
372#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
373#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
374#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
375#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
376#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
377#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
378#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
379#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
380#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Dipen Dudhat2f143ed2011-07-28 14:47:28 -0500381#endif
382
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000383/* CPLD on IFC */
384#define CONFIG_SYS_CPLD_BASE 0xffb00000
385
386#ifdef CONFIG_PHYS_64BIT
387#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
388#else
389#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
390#endif
391
392#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
393 | CSPR_PORT_SIZE_8 \
394 | CSPR_MSEL_GPCM \
395 | CSPR_V)
396#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
397#define CONFIG_SYS_CSOR3 0x0
398/* CPLD Timing parameters for IFC CS3 */
399#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
400 FTIM0_GPCM_TEADC(0x0e) | \
401 FTIM0_GPCM_TEAHC(0x0e))
402#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
403 FTIM1_GPCM_TRAD(0x1f))
404#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiec2bc4602014-06-26 14:41:33 +0800405 FTIM2_GPCM_TCH(0x8) | \
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000406 FTIM2_GPCM_TWP(0x1f))
407#define CONFIG_SYS_CS3_FTIM3 0x0
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000408
Aneesh Bansala40370d2014-03-07 19:12:09 +0530409#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
410 defined(CONFIG_RAMBOOT_NAND)
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000411#define CONFIG_SYS_RAMBOOT
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000412#else
413#undef CONFIG_SYS_RAMBOOT
414#endif
415
Prabhakar Kushwahad324f472013-04-16 13:27:44 +0530416#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Aneesh Bansalc24c0f32014-01-20 14:57:03 +0530417#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwahad324f472013-04-16 13:27:44 +0530418#define CONFIG_A003399_NOR_WORKAROUND
419#endif
420#endif
421
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000422#define CONFIG_SYS_INIT_RAM_LOCK
423#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
York Sun515fbb42016-04-06 13:22:10 -0700424#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000425
York Sun515fbb42016-04-06 13:22:10 -0700426#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000427 - GENERATED_GBL_DATA_SIZE)
428#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
429
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530430#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000431
Ying Zhang1233cbc2014-01-24 15:50:09 +0800432/*
433 * Config the L2 Cache as L2 SRAM
434 */
435#if defined(CONFIG_SPL_BUILD)
436#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
437#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
438#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
439#define CONFIG_SYS_L2_SIZE (256 << 10)
440#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
441#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
442#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhang1233cbc2014-01-24 15:50:09 +0800443#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
444#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
445#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
Miquel Raynald0935362019-10-03 19:50:03 +0200446#elif defined(CONFIG_MTD_RAW_NAND)
Ying Zhang1233cbc2014-01-24 15:50:09 +0800447#ifdef CONFIG_TPL_BUILD
448#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
449#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
450#define CONFIG_SYS_L2_SIZE (256 << 10)
451#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
452#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
453#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
454#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
455#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
456#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
457#else
458#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
459#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
460#define CONFIG_SYS_L2_SIZE (256 << 10)
461#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
462#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
463#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
464#endif
465#endif
466#endif
467
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000468/* Serial Port */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000469#undef CONFIG_SERIAL_SOFTWARE_FIFO
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000470#define CONFIG_SYS_NS16550_SERIAL
471#define CONFIG_SYS_NS16550_REG_SIZE 1
472#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhang1233cbc2014-01-24 15:50:09 +0800473#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Dipen Dudhat2f143ed2011-07-28 14:47:28 -0500474#define CONFIG_NS16550_MIN_FUNCTIONS
475#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000476
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000477#define CONFIG_SYS_BAUDRATE_TABLE \
478 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
479
480#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
481#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
482
Heiko Schocherf2850742012-10-24 13:48:22 +0200483/* I2C */
Shengzhou Liu36446ef2013-09-13 14:46:02 +0800484#define I2C_PCA9557_ADDR1 0x18
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800485#define I2C_PCA9557_ADDR2 0x19
Shengzhou Liu36446ef2013-09-13 14:46:02 +0800486#define I2C_PCA9557_BUS_NUM 0
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000487
488/* I2C EEPROM */
York Sun7f945ca2016-11-16 13:30:06 -0800489#if defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800490#ifdef CONFIG_ID_EEPROM
491#define CONFIG_SYS_I2C_EEPROM_NXID
492#endif
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800493#define CONFIG_SYS_EEPROM_BUS_NUM 0
494#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
495#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000496/* enable read and write access to EEPROM */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000497
498/* RTC */
499#define CONFIG_RTC_PT7C4338
500#define CONFIG_SYS_I2C_RTC_ADDR 0x68
501
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000502/*
503 * SPI interface will not be available in case of NAND boot SPI CS0 will be
504 * used for SLIC
505 */
Miquel Raynald0935362019-10-03 19:50:03 +0200506#if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT)
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000507/* eSPI - Enhanced SPI */
Dipen Dudhat2f143ed2011-07-28 14:47:28 -0500508#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000509
510#if defined(CONFIG_TSEC_ENET)
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000511#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
512#define CONFIG_TSEC1 1
513#define CONFIG_TSEC1_NAME "eTSEC1"
514#define CONFIG_TSEC2 1
515#define CONFIG_TSEC2_NAME "eTSEC2"
516#define CONFIG_TSEC3 1
517#define CONFIG_TSEC3_NAME "eTSEC3"
518
519#define TSEC1_PHY_ADDR 1
520#define TSEC2_PHY_ADDR 0
521#define TSEC3_PHY_ADDR 2
522
523#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
524#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
525#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
526
527#define TSEC1_PHYIDX 0
528#define TSEC2_PHYIDX 0
529#define TSEC3_PHYIDX 0
530
531#define CONFIG_ETHPRIME "eTSEC1"
532
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000533/* TBI PHY configuration for SGMII mode */
534#define CONFIG_TSEC_TBICR_SETTINGS ( \
535 TBICR_PHY_RESET \
536 | TBICR_ANEG_ENABLE \
537 | TBICR_FULL_DUPLEX \
538 | TBICR_SPEED1_SET \
539 )
540
541#endif /* CONFIG_TSEC_ENET */
542
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000543/* SATA */
Zang Roy-R619112ce421a2012-11-26 00:05:38 +0000544#define CONFIG_FSL_SATA_V2
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000545
546#ifdef CONFIG_FSL_SATA
547#define CONFIG_SYS_SATA_MAX_DEVICE 2
548#define CONFIG_SATA1
549#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
550#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
551#define CONFIG_SATA2
552#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
553#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
554
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000555#define CONFIG_LBA48
556#endif /* #ifdef CONFIG_FSL_SATA */
557
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000558#ifdef CONFIG_MMC
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000559#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
560#endif
561
562#define CONFIG_HAS_FSL_DR_USB
563
564#if defined(CONFIG_HAS_FSL_DR_USB)
Tom Riniceed5d22017-05-12 22:33:27 -0400565#ifdef CONFIG_USB_EHCI_HCD
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000566#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000567#endif
568#endif
569
570/*
571 * Environment
572 */
Ying Zhang1233cbc2014-01-24 15:50:09 +0800573#if defined(CONFIG_SDCARD)
Fabio Estevamae8c45e2012-01-11 09:20:50 +0000574#define CONFIG_FSL_FIXED_MMC_LOCATION
Miquel Raynald0935362019-10-03 19:50:03 +0200575#elif defined(CONFIG_MTD_RAW_NAND)
Ying Zhang1233cbc2014-01-24 15:50:09 +0800576#ifdef CONFIG_TPL_BUILD
Tom Rini5cd7ece2019-11-18 20:02:10 -0500577#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
Ying Zhang1233cbc2014-01-24 15:50:09 +0800578#else
York Sun7f945ca2016-11-16 13:30:06 -0800579#if defined(CONFIG_TARGET_P1010RDB_PA)
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800580#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
York Sun7f945ca2016-11-16 13:30:06 -0800581#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800582#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
583#endif
Ying Zhang1233cbc2014-01-24 15:50:09 +0800584#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000585#endif
586
587#define CONFIG_LOADS_ECHO /* echo on for serial download */
588#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
589
Tom Riniceed5d22017-05-12 22:33:27 -0400590#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000591 || defined(CONFIG_FSL_SATA)
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000592#endif
593
594/*
595 * Miscellaneous configurable options
596 */
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000597
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000598/*
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000599 * For booting Linux, the board info and command line data
600 * have to be in the first 64 MB of memory, since this is
601 * the maximum mapped by the Linux kernel during initialization.
602 */
603#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
604#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
605
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000606/*
607 * Environment Configuration
608 */
609
610#if defined(CONFIG_TSEC_ENET)
611#define CONFIG_HAS_ETH0
612#define CONFIG_HAS_ETH1
613#define CONFIG_HAS_ETH2
614#endif
615
Joe Hershberger257ff782011-10-13 13:03:47 +0000616#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000617#define CONFIG_BOOTFILE "uImage"
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000618#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
619
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000620#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200621 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000622 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200623 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000624 "loadaddr=1000000\0" \
625 "consoledev=ttyS0\0" \
626 "ramdiskaddr=2000000\0" \
627 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500628 "fdtaddr=1e00000\0" \
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000629 "fdtfile=p1010rdb.dtb\0" \
630 "bdev=sda1\0" \
631 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
632 "othbootargs=ramdisk_size=600000\0" \
633 "usbfatboot=setenv bootargs root=/dev/ram rw " \
634 "console=$consoledev,$baudrate $othbootargs; " \
635 "usb start;" \
636 "fatload usb 0:2 $loadaddr $bootfile;" \
637 "fatload usb 0:2 $fdtaddr $fdtfile;" \
638 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
639 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
640 "usbext2boot=setenv bootargs root=/dev/ram rw " \
641 "console=$consoledev,$baudrate $othbootargs; " \
642 "usb start;" \
643 "ext2load usb 0:4 $loadaddr $bootfile;" \
644 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
645 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800646 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
647 CONFIG_BOOTMODE
648
York Sun7f945ca2016-11-16 13:30:06 -0800649#if defined(CONFIG_TARGET_P1010RDB_PA)
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800650#define CONFIG_BOOTMODE \
651 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
652 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
653 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
654 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
655 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
656 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
657
York Sun7f945ca2016-11-16 13:30:06 -0800658#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liuf0af4382013-09-13 14:46:03 +0800659#define CONFIG_BOOTMODE \
660 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
661 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
662 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
663 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
664 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
665 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
666 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
667 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
668 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
669 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
670#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000671
Ruchika Guptab36ccc52011-06-08 22:52:48 -0500672#include <asm/fsl_secure_boot.h>
Ruchika Guptab36ccc52011-06-08 22:52:48 -0500673
Poonam Aggrwala2ec1352011-02-09 19:17:53 +0000674#endif /* __CONFIG_H */