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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
jason56ef75c2013-11-06 22:59:08 +08002/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
TsiChung Liewdd8513c2008-07-23 17:11:47 -05003 * Hayden Fraser (Hayden.Fraser@freescale.com)
TsiChung Liewdd8513c2008-07-23 17:11:47 -05004 */
5
6#ifndef _M5253DEMO_H
7#define _M5253DEMO_H
8
Simon Glassfb64e362020-05-10 11:40:09 -06009#include <linux/stringify.h>
10
TsiChung Liewdd8513c2008-07-23 17:11:47 -050011#define CONFIG_MCFTMR
12
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020013#define CONFIG_SYS_UART_PORT (0)
TsiChung Liewdd8513c2008-07-23 17:11:47 -050014
TsiChung Liewdd8513c2008-07-23 17:11:47 -050015
16/* Configuration for environment
17 * Environment is embedded in u-boot in the second sector of the flash
18 */
TsiChung Liewdd8513c2008-07-23 17:11:47 -050019
angelo@sysam.it6312a952015-03-29 22:54:16 +020020#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060021 . = DEFINED(env_offset) ? env_offset : .; \
22 env/embedded.o(.text*);
angelo@sysam.it6312a952015-03-29 22:54:16 +020023
Simon Glassb569a012017-05-17 03:25:30 -060024#ifdef CONFIG_IDE
TsiChung Liewdd8513c2008-07-23 17:11:47 -050025/* ATA */
TsiChung Liewdd8513c2008-07-23 17:11:47 -050026# define CONFIG_IDE_RESET 1
27# define CONFIG_IDE_PREINIT 1
28# define CONFIG_ATAPI
29# undef CONFIG_LBA48
30
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020031# define CONFIG_SYS_IDE_MAXBUS 1
32# define CONFIG_SYS_IDE_MAXDEVICE 2
TsiChung Liewdd8513c2008-07-23 17:11:47 -050033
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
35# define CONFIG_SYS_ATA_IDE0_OFFSET 0
TsiChung Liewdd8513c2008-07-23 17:11:47 -050036
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
38# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
39# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
40# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
TsiChung Liewdd8513c2008-07-23 17:11:47 -050041#endif
42
43#define CONFIG_DRIVER_DM9000
44#ifdef CONFIG_DRIVER_DM9000
TsiChung Liew7f1a0462008-10-21 10:03:07 +000045# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
TsiChung Liewdd8513c2008-07-23 17:11:47 -050046# define DM9000_IO CONFIG_DM9000_BASE
47# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
48# undef CONFIG_DM9000_DEBUG
Jason Jina2fabf12011-08-19 10:18:15 +080049# define CONFIG_DM9000_BYTE_SWAPPED
TsiChung Liewdd8513c2008-07-23 17:11:47 -050050
TsiChung Liewdd8513c2008-07-23 17:11:47 -050051# define CONFIG_OVERWRITE_ETHADDR_ONCE
52
53# define CONFIG_EXTRA_ENV_SETTINGS \
54 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +020055 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liewdd8513c2008-07-23 17:11:47 -050056 "loadaddr=10000\0" \
57 "u-boot=u-boot.bin\0" \
58 "load=tftp ${loadaddr) ${u-boot}\0" \
59 "upd=run load; run prog\0" \
TsiChung Liew3dd72f62010-03-10 11:56:36 -060060 "prog=prot off 0xff800000 0xff82ffff;" \
61 "era 0xff800000 0xff82ffff;" \
TsiChung Liew0212f742010-03-15 19:39:21 -050062 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
TsiChung Liewdd8513c2008-07-23 17:11:47 -050063 "save\0" \
64 ""
65#endif
66
Mario Six790d8442018-03-28 14:38:20 +020067#define CONFIG_HOSTNAME "M5253DEMO"
TsiChung Liewdd8513c2008-07-23 17:11:47 -050068
TsiChung Liew0c1e3252008-08-19 03:01:19 +060069/* I2C */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
71#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
72#define CONFIG_SYS_I2C_PINMUX_SET (0)
TsiChung Liew0c1e3252008-08-19 03:01:19 +060073
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
75#define CONFIG_SYS_FAST_CLK
76#ifdef CONFIG_SYS_FAST_CLK
77# define CONFIG_SYS_PLLCR 0x1243E054
78# define CONFIG_SYS_CLK 140000000
TsiChung Liewdd8513c2008-07-23 17:11:47 -050079#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080# define CONFIG_SYS_PLLCR 0x135a4140
81# define CONFIG_SYS_CLK 70000000
TsiChung Liewdd8513c2008-07-23 17:11:47 -050082#endif
83
84/*
85 * Low Level Configuration Settings
86 * (address mappings, register initial values, etc.)
87 * You should know what you are doing if you make changes here.
88 */
89
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
91#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
TsiChung Liewdd8513c2008-07-23 17:11:47 -050092
93/*
94 * Definitions for initial stack pointer and data area (in DPRAM)
95 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020097#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +020098#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500100
101/*
102 * Start addresses for the final memory configuration
103 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500105 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_SDRAM_BASE 0x00000000
107#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500108
109#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110# define CONFIG_SYS_MONITOR_BASE 0x20000
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500111#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500113#endif
114
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115#define CONFIG_SYS_MONITOR_LEN 0x40000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500117
118/*
119 * For booting Linux, the board info and command line data
120 * have to be in the first 8 MB of memory, since this is
121 * the maximum mapped by the Linux kernel during initialization ??
122 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew25a00632009-01-27 12:57:47 +0000124#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500125
126/* FLASH organization */
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000127#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
129#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500130
131#define FLASH_SST6401B 0x200
132#define SST_ID_xF6401B 0x236D236D
133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500135/*
136 * Unable to use CFI driver, due to incompatible sector erase command by SST.
137 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
138 * 0x30 is block erase in SST
139 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140# define CONFIG_SYS_FLASH_SIZE 0x800000
141# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500142# define CONFIG_FLASH_CFI_LEGACY
143#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144# define CONFIG_SYS_SST_SECT 2048
145# define CONFIG_SYS_SST_SECTSZ 0x1000
146# define CONFIG_SYS_FLASH_WRITE_TOUT 500
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500147#endif
148
149/* Cache Configuration */
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500150
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600151#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200152 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600153#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200154 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600155#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
156#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
157 CF_ADDRMASK(8) | \
158 CF_ACR_EN | CF_ACR_SM_ALL)
159#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
160 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
161 CF_ACR_EN | CF_ACR_SM_ALL)
162#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
163 CF_CACR_DBWE)
164
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500165/* Port configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_SYS_FECI2C 0xF0
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500167
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000168#define CONFIG_SYS_CS0_BASE 0xFF800000
169#define CONFIG_SYS_CS0_MASK 0x007F0021
170#define CONFIG_SYS_CS0_CTRL 0x00001D80
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500171
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000172#define CONFIG_SYS_CS1_BASE 0xE0000000
173#define CONFIG_SYS_CS1_MASK 0x00000001
174#define CONFIG_SYS_CS1_CTRL 0x00003DD8
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500175
176/*-----------------------------------------------------------------------
177 * Port configuration
178 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
180#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
181#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
182#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
183#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
184#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
185#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
TsiChung Liewdd8513c2008-07-23 17:11:47 -0500186
187#endif /* _M5253DEMO_H */