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git01.mediatek.com / filogic / uboot / d6d7adb02e08e070859ebab8d891f9206ea68a23 / . / configs / P1020RDB-PC_36BIT_SPIFLASH_defconfig
blob: c5a64de98e08900c11002cd44460f79ac6cf4946 [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_PPC=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0x11001000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]3CONFIG_SYS_MALLOC_LEN=0x100000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]4CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]5CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]6CONFIG_ENV_SIZE=0x2000
7CONFIG_ENV_OFFSET=0x100000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]8CONFIG_ENV_SECT_SIZE=0x10000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]10CONFIG_SPL_TEXT_BASE=0xf8f81000
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]11CONFIG_SPL_SERIAL=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]12CONFIG_SPL=y
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]13CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]14CONFIG_SPL_SPI=y
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]15CONFIG_MPC85xx=y
Simon Glass9fdc0de2017-05-17 03:25:15 -0600[diff] [blame]16# CONFIG_CMD_ERRATA is not set
York Sun443108bf2016-11-17 13:52:44 -0800[diff] [blame]17CONFIG_TARGET_P1020RDB_PC=y
Masahiro Yamada653e9fe2016-07-25 19:56:03 +0900[diff] [blame]18CONFIG_PHYS_64BIT=y
Tom Rini5ca768d2022-01-24 21:08:41 +0000[diff] [blame]19CONFIG_MP=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]20CONFIG_FIT=y
21CONFIG_FIT_VERBOSE=y
22CONFIG_OF_BOARD_SETUP=y
23CONFIG_OF_STDOUT_VIA_ALIAS=y
York Sun443108bf2016-11-17 13:52:44 -0800[diff] [blame]24CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]25CONFIG_BOOTDELAY=10
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]26CONFIG_USE_BOOTCOMMAND=y
27CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw rootdelay=30 console=$consoledev,$baudrate $othbootargs;usb start;ext2load usb 0:1 $loadaddr /boot/$bootfile;ext2load usb 0:1 $fdtaddr /boot/$fdtfile;bootm $loadaddr - $fdtaddr"
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]28CONFIG_BOARD_EARLY_INIT_F=y
Mario Six75b23ed2018-03-28 14:38:15 +0200[diff] [blame]29CONFIG_BOARD_EARLY_INIT_R=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]30# CONFIG_MISC_INIT_R is not set
Tom Rini623d67e2018-02-06 12:15:38 -0500[diff] [blame]31# CONFIG_SPL_FRAMEWORK is not set
Tom Rinie5678e42019-06-01 14:20:25 -0400[diff] [blame]32CONFIG_SPL_SPI_BOOT=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]33CONFIG_SPL_ENV_SUPPORT=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]34CONFIG_SPL_I2C=y
Simon Glass64571062021-08-08 12:20:16 -0600[diff] [blame]35CONFIG_SPL_MPC8XXX_INIT_DDR=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]36CONFIG_HUSH_PARSER=y
Adam Ford58dbf862018-02-06 07:58:59 -0600[diff] [blame]37# CONFIG_AUTO_COMPLETE is not set
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]38CONFIG_CMD_IMLS=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]39CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
40CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]41CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]42CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]43CONFIG_CMD_USB=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]44CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]45CONFIG_CMD_PING=y
Simon Glass027608e2017-05-17 03:25:25 -0600[diff] [blame]46# CONFIG_CMD_HASH is not set
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]47CONFIG_CMD_EXT2=y
48CONFIG_CMD_FAT=y
Hou Zhiqiang224999f2019-08-20 09:35:28 +0000[diff] [blame]49CONFIG_OF_CONTROL=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]50CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]51CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]52CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]53CONFIG_DM=y
Tom Rinif7246c22021-08-21 13:50:17 -0400[diff] [blame]54CONFIG_DDR_CLK_FREQ=66666666
Tom Rinif7eed202021-11-13 18:10:40 -0500[diff] [blame]55CONFIG_SYS_BR0_PRELIM_BOOL=y
56CONFIG_SYS_BR0_PRELIM=0xEF001001
57CONFIG_SYS_OR0_PRELIM=0xFC000FF7
58CONFIG_SYS_BR2_PRELIM_BOOL=y
59CONFIG_SYS_BR2_PRELIM=0xFFB00801
60CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
61CONFIG_SYS_BR3_PRELIM_BOOL=y
62CONFIG_SYS_BR3_PRELIM=0xFFA00801
63CONFIG_SYS_OR3_PRELIM=0xFFF009F7
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]64CONFIG_DM_I2C=y
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]65CONFIG_SPL_SYS_I2C_LEGACY=y
Tom Rinib1b13072021-08-18 23:12:37 -0400[diff] [blame]66CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
Tom Rinibe94c762021-08-18 23:12:35 -0400[diff] [blame]67CONFIG_SYS_I2C_FSL=y
68CONFIG_SYS_FSL_I2C_OFFSET=0x3000
69CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
70CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]71CONFIG_SYS_I2C_EEPROM_ADDR=0x52
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]72CONFIG_FSL_ESDHC=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]73CONFIG_MTD=y
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame]74CONFIG_MTD_NOR_FLASH=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]75CONFIG_FLASH_CFI_DRIVER=y
76CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
77CONFIG_SYS_FLASH_CFI=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]78CONFIG_DM_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]79CONFIG_SF_DEFAULT_SPEED=10000000
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]80CONFIG_SPI_FLASH_SPANSION=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]81CONFIG_PHY_ATHEROS=y
82CONFIG_PHY_BROADCOM=y
83CONFIG_PHY_DAVICOM=y
84CONFIG_PHY_LXT=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]85CONFIG_PHY_MARVELL=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]86CONFIG_PHY_NATSEMI=y
87CONFIG_PHY_REALTEK=y
88CONFIG_PHY_SMSC=y
89CONFIG_PHY_VITESSE=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]90CONFIG_PHY_FIXED=y
91CONFIG_DM_ETH=y
92CONFIG_DM_MDIO=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]93CONFIG_PHY_GIGE=y
Simon Glass9008a5b2015-08-19 09:33:43 -0600[diff] [blame]94CONFIG_E1000=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]95CONFIG_MII=y
96CONFIG_TSEC_ENET=y
Hou Zhiqiang38853312019-08-27 11:04:11 +0000[diff] [blame]97CONFIG_PCIE_FSL=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]98CONFIG_DM_RTC=y
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]99CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]100CONFIG_SPI=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]101CONFIG_DM_SPI=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]102CONFIG_FSL_ESPI=y
Tom Rini6e9cb112016-09-08 16:31:26 -0400[diff] [blame]103CONFIG_USB=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]104CONFIG_USB_EHCI_FSL=y
Tom Rini526e3c82020-10-05 13:11:41 -0400[diff] [blame]105CONFIG_USB_STORAGE=y
Marek Szyprowski795dc7d2020-06-03 14:43:40 +0200[diff] [blame]106CONFIG_ADDR_MAP=y