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git01.mediatek.com / filogic / uboot / d6a4077e61fbf3b97fa3280fd99aa56225e74ddb / . / drivers / clk / sunxi / clk_a23.c
blob: d94fecadd59a0d5fea83b426f2ecdfa85b1ad0ed [file] [log] [blame]
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions B.V.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame]11#include <clk/sunxi.h>
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]12#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
13#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]15
16static struct ccu_clk_gate a23_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
23 [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
24 [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
25
Andre Przywara3e9aa0b2022-05-04 22:10:28 +0100[diff] [blame]26 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
27
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]28 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
29 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
30 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]31 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
32 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
33 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
34 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
35 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
36
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]37 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
38 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
39
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]40 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
41 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
42 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
43 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
44 [CLK_USB_OHCI] = GATE(0x0cc, BIT(16)),
45};
46
47static struct ccu_reset a23_resets[] = {
48 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
49 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
50 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
51
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]52 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
53 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
54 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]55 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
56 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]57 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
58 [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
59 [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]60
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]61 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
62 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
63 [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]64 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
65 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
66 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
67 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
68 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]69};
70
Samuel Holland751c6c62022-05-09 00:29:34 -0500[diff] [blame]71const struct ccu_desc a23_ccu_desc = {
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]72 .gates = a23_gates,
73 .resets = a23_resets,
Samuel Holland84436502022-05-09 00:29:31 -0500[diff] [blame]74 .num_gates = ARRAY_SIZE(a23_gates),
75 .num_resets = ARRAY_SIZE(a23_resets),
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]76};