Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 12e3faa22d5a0a49918a68bf0555c30150dbadb6 / . / drivers / clk / sunxi / clk_a23.c
blob: 52de1cb8d4b3404932748e1771ffbf3993c8bd23 [file] [log] [blame]
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions B.V.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame^]11#include <clk/sunxi.h>
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]12#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
13#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]15
16static struct ccu_clk_gate a23_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
23 [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
24 [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
25
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]26 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
27 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
28 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
29 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
30 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
31
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]32 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
33 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
34
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]35 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
36 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
37 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
38 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
39 [CLK_USB_OHCI] = GATE(0x0cc, BIT(16)),
40};
41
42static struct ccu_reset a23_resets[] = {
43 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
44 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
45 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
46
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]47 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
48 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
49 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]50 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
51 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]52 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
53 [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
54 [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]55
56 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
57 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
58 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
59 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
60 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]61};
62
63static const struct ccu_desc a23_ccu_desc = {
64 .gates = a23_gates,
65 .resets = a23_resets,
66};
67
68static int a23_clk_bind(struct udevice *dev)
69{
70 return sunxi_reset_bind(dev, ARRAY_SIZE(a23_resets));
71}
72
73static const struct udevice_id a23_clk_ids[] = {
74 { .compatible = "allwinner,sun8i-a23-ccu",
75 .data = (ulong)&a23_ccu_desc },
76 { .compatible = "allwinner,sun8i-a33-ccu",
77 .data = (ulong)&a23_ccu_desc },
78 { }
79};
80
81U_BOOT_DRIVER(clk_sun8i_a23) = {
82 .name = "sun8i_a23_ccu",
83 .id = UCLASS_CLK,
84 .of_match = a23_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]85 .priv_auto = sizeof(struct ccu_priv),
Jagan Teki885abd82018-08-02 23:25:03 +0530[diff] [blame]86 .ops = &sunxi_clk_ops,
87 .probe = sunxi_clk_probe,
88 .bind = a23_clk_bind,
89};