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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Hannes Petermaierfb003662014-02-07 08:07:36 +01002/*
3 * bur_am335x_common.h
4 *
5 * common parts used by B&R AM335x based boards
6 *
Hannes Schmelzer27bf4412016-02-19 12:09:45 +01007 * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
Hannes Petermaierfb003662014-02-07 08:07:36 +01008 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
Hannes Petermaierfb003662014-02-07 08:07:36 +01009 */
10
11#ifndef __BUR_AM335X_COMMON_H__
12#define __BUR_AM335X_COMMON_H__
13/* ------------------------------------------------------------------------- */
Hannes Schmelzer5639eeb2018-07-06 15:41:28 +020014
15/* legacy #defines for non DM bur-board */
16#ifndef CONFIG_DM
17#define CONFIG_SYS_NS16550_SERIAL
18#define CONFIG_SYS_NS16550_REG_SIZE (-4)
19#define CONFIG_SYS_NS16550_CLK (48000000)
20#define CONFIG_SYS_NS16550_COM1 0x44e09000
21
Simon Glass0529b592021-07-10 21:14:32 -060022#define CONFIG_SYS_I2C_LEGACY
Hannes Schmelzer5639eeb2018-07-06 15:41:28 +020023
24#endif /* CONFIG_DM */
25
Hannes Petermaierfb003662014-02-07 08:07:36 +010026#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
27
28/* Timer information */
29#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
30#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
Hannes Petermaierfb003662014-02-07 08:07:36 +010031#define CONFIG_POWER_TPS65217
32
Hannes Petermaierfb003662014-02-07 08:07:36 +010033#include <asm/arch/omap.h>
34
Hannes Petermaierfb003662014-02-07 08:07:36 +010035/*
36 * SPL related defines. The Public RAM memory map the ROM defines the
37 * area between 0x402F0400 and 0x4030B800 as a download area and
38 * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
39 * supports X-MODEM loading via UART, and we leverage this and then use
Tom Rinicfff4aa2016-08-26 13:30:43 -040040 * Y-MODEM to load u-boot.img, when booted over UART. We must also include
41 * the scratch space that U-Boot uses in SRAM.
Hannes Petermaierfb003662014-02-07 08:07:36 +010042 */
Tom Rinicfff4aa2016-08-26 13:30:43 -040043#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
44 CONFIG_SPL_TEXT_BASE)
Hannes Petermaierfb003662014-02-07 08:07:36 +010045
46/*
47 * Since SPL did pll and ddr initialization for us,
48 * we don't need to do it twice.
49 */
50#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
51#define CONFIG_SKIP_LOWLEVEL_INIT
52#endif /* !CONFIG_SPL_BUILD, ... */
53/*
54 * Our DDR memory always starts at 0x80000000 and U-Boot shall have
55 * relocated itself to higher in memory by the time this value is used.
56 */
57#define CONFIG_SYS_LOAD_ADDR 0x80000000
58/*
59 * ----------------------------------------------------------------------------
60 * DDR information. We say (for simplicity) that we have 1 bank,
61 * always, even when we have more. We always start at 0x80000000,
62 * and we place the initial stack pointer in our SRAM.
63 */
Hannes Petermaierfb003662014-02-07 08:07:36 +010064#define CONFIG_SYS_SDRAM_BASE 0x80000000
65#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
66 GENERATED_GBL_DATA_SIZE)
67
Hannes Petermaierfb003662014-02-07 08:07:36 +010068/*
69 * Our platforms make use of SPL to initalize the hardware (primarily
70 * memory) enough for full U-Boot to be loaded. We also support Falcon
71 * Mode so that the Linux kernel can be booted directly from SPL
72 * instead, if desired. We make use of the general SPL framework found
73 * under common/spl/. Given our generally common memory map, we set a
74 * number of related defaults and sizes here.
75 */
Hannes Petermaierfb003662014-02-07 08:07:36 +010076/*
77 * Place the image at the start of the ROM defined image space.
78 * We limit our size to the ROM-defined downloaded image area, and use the
79 * rest of the space for stack. We load U-Boot itself into memory at
80 * 0x80800000 for legacy reasons (to not conflict with older SPLs). We
81 * have our BSS be placed 1MiB after this, to allow for the default
82 * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
83 * We have the SPL malloc pool at the end of the BSS area.
84 *
85 * ----------------------------------------------------------------------------
86 */
Hannes Petermaierfb003662014-02-07 08:07:36 +010087#define CONFIG_SPL_BSS_START_ADDR 0x80A00000
88#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
89#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
90 CONFIG_SPL_BSS_MAX_SIZE)
91#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
92
93/* General parts of the framework, required. */
Hannes Petermaierfb003662014-02-07 08:07:36 +010094
95#endif /* ! __BUR_AM335X_COMMON_H__ */