blob: 35df413321fe695d5d5fc0dc220715c754191577 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk12490652004-04-18 21:13:41 +00002/*
Michal Simek7e4372a2015-12-01 14:24:20 +01003 * (C) Copyright 2008 - 2015 Michal Simek <monstr@monstr.eu>
Michal Simek403d6192008-07-11 10:10:31 +02004 * Clean driver and add xilinx constant from header file
wdenk12490652004-04-18 21:13:41 +00005 *
Michal Simek403d6192008-07-11 10:10:31 +02006 * (C) Copyright 2004 Atmark Techno, Inc.
wdenk12490652004-04-18 21:13:41 +00007 * Yasushi SHOJI <yashi@atmark-techno.com>
wdenk12490652004-04-18 21:13:41 +00008 */
9
10#include <config.h>
Michal Simek75348da2011-09-25 21:03:08 +000011#include <common.h>
Michal Simek7e4372a2015-12-01 14:24:20 +010012#include <dm.h>
Michal Simek403d6192008-07-11 10:10:31 +020013#include <asm/io.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Michal Simek75348da2011-09-25 21:03:08 +000015#include <linux/compiler.h>
16#include <serial.h>
wdenk12490652004-04-18 21:13:41 +000017
Michal Simek7e4372a2015-12-01 14:24:20 +010018#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */
19#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */
20#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */
21#define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */
wdenk12490652004-04-18 21:13:41 +000022
Michal Simeke5b3c1d2014-01-21 07:29:47 +010023#define ULITE_CONTROL_RST_TX 0x01
24#define ULITE_CONTROL_RST_RX 0x02
25
Michal Simek8e4e5f02024-02-14 12:52:32 +010026static bool little_endian __section(".data");
T Karthik Reddy070ffd22020-08-14 03:02:15 -060027
Michal Simek75348da2011-09-25 21:03:08 +000028struct uartlite {
29 unsigned int rx_fifo;
30 unsigned int tx_fifo;
31 unsigned int status;
Michal Simeke5b3c1d2014-01-21 07:29:47 +010032 unsigned int control;
Michal Simek75348da2011-09-25 21:03:08 +000033};
34
Simon Glassb75b15b2020-12-03 16:55:23 -070035struct uartlite_plat {
Michal Simek7e4372a2015-12-01 14:24:20 +010036 struct uartlite *regs;
Michal Simek75348da2011-09-25 21:03:08 +000037};
38
T Karthik Reddy070ffd22020-08-14 03:02:15 -060039static u32 uart_in32(void __iomem *addr)
40{
41 if (little_endian)
42 return in_le32(addr);
43 else
44 return in_be32(addr);
45}
46
47static void uart_out32(void __iomem *addr, u32 val)
48{
49 if (little_endian)
50 out_le32(addr, val);
51 else
52 out_be32(addr, val);
53}
54
Michal Simek7e4372a2015-12-01 14:24:20 +010055static int uartlite_serial_putc(struct udevice *dev, const char ch)
Michal Simek75348da2011-09-25 21:03:08 +000056{
Simon Glassb75b15b2020-12-03 16:55:23 -070057 struct uartlite_plat *plat = dev_get_plat(dev);
Michal Simek7e4372a2015-12-01 14:24:20 +010058 struct uartlite *regs = plat->regs;
Michal Simek75348da2011-09-25 21:03:08 +000059
T Karthik Reddy070ffd22020-08-14 03:02:15 -060060 if (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
Michal Simek7e4372a2015-12-01 14:24:20 +010061 return -EAGAIN;
Michal Simek75348da2011-09-25 21:03:08 +000062
T Karthik Reddy070ffd22020-08-14 03:02:15 -060063 uart_out32(&regs->tx_fifo, ch & 0xff);
Michal Simek75348da2011-09-25 21:03:08 +000064
Michal Simek7e4372a2015-12-01 14:24:20 +010065 return 0;
Michal Simek75348da2011-09-25 21:03:08 +000066}
67
Michal Simek7e4372a2015-12-01 14:24:20 +010068static int uartlite_serial_getc(struct udevice *dev)
Michal Simek75348da2011-09-25 21:03:08 +000069{
Simon Glassb75b15b2020-12-03 16:55:23 -070070 struct uartlite_plat *plat = dev_get_plat(dev);
Michal Simek7e4372a2015-12-01 14:24:20 +010071 struct uartlite *regs = plat->regs;
72
T Karthik Reddy070ffd22020-08-14 03:02:15 -060073 if (!(uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA))
Michal Simek7e4372a2015-12-01 14:24:20 +010074 return -EAGAIN;
Michal Simek75348da2011-09-25 21:03:08 +000075
T Karthik Reddy070ffd22020-08-14 03:02:15 -060076 return uart_in32(&regs->rx_fifo) & 0xff;
Michal Simek75348da2011-09-25 21:03:08 +000077}
78
Michal Simek7e4372a2015-12-01 14:24:20 +010079static int uartlite_serial_pending(struct udevice *dev, bool input)
Michal Simek75348da2011-09-25 21:03:08 +000080{
Simon Glassb75b15b2020-12-03 16:55:23 -070081 struct uartlite_plat *plat = dev_get_plat(dev);
Michal Simek7e4372a2015-12-01 14:24:20 +010082 struct uartlite *regs = plat->regs;
wdenk12490652004-04-18 21:13:41 +000083
Michal Simek7e4372a2015-12-01 14:24:20 +010084 if (input)
T Karthik Reddy070ffd22020-08-14 03:02:15 -060085 return uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA;
Michal Simek7e4372a2015-12-01 14:24:20 +010086
T Karthik Reddy070ffd22020-08-14 03:02:15 -060087 return !(uart_in32(&regs->status) & SR_TX_FIFO_EMPTY);
Michal Simek75348da2011-09-25 21:03:08 +000088}
89
Michal Simek7e4372a2015-12-01 14:24:20 +010090static int uartlite_serial_probe(struct udevice *dev)
Michal Simekd40a2522012-07-02 10:32:18 +020091{
Simon Glassb75b15b2020-12-03 16:55:23 -070092 struct uartlite_plat *plat = dev_get_plat(dev);
Michal Simek7e4372a2015-12-01 14:24:20 +010093 struct uartlite *regs = plat->regs;
T Karthik Reddy070ffd22020-08-14 03:02:15 -060094 int ret;
Michal Simeke5b3c1d2014-01-21 07:29:47 +010095
T Karthik Reddy070ffd22020-08-14 03:02:15 -060096 uart_out32(&regs->control, 0);
97 uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
98 ret = uart_in32(&regs->status);
99 /* Endianness detection */
100 if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
101 little_endian = true;
102 uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
103 ULITE_CONTROL_RST_TX);
104 }
Michal Simeke5b3c1d2014-01-21 07:29:47 +0100105
Michal Simek7e4372a2015-12-01 14:24:20 +0100106 return 0;
Michal Simekd40a2522012-07-02 10:32:18 +0200107}
108
Simon Glassaad29ae2020-12-03 16:55:21 -0700109static int uartlite_serial_of_to_plat(struct udevice *dev)
Michal Simek7e4372a2015-12-01 14:24:20 +0100110{
Simon Glassb75b15b2020-12-03 16:55:23 -0700111 struct uartlite_plat *plat = dev_get_plat(dev);
Michal Simek7e4372a2015-12-01 14:24:20 +0100112
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900113 plat->regs = dev_read_addr_ptr(dev);
Michal Simek75348da2011-09-25 21:03:08 +0000114
Michal Simek7e4372a2015-12-01 14:24:20 +0100115 return 0;
Marek Vasut5bcdf242012-09-09 18:48:28 +0200116}
Michal Simek75348da2011-09-25 21:03:08 +0000117
Michal Simek7e4372a2015-12-01 14:24:20 +0100118static const struct dm_serial_ops uartlite_serial_ops = {
119 .putc = uartlite_serial_putc,
120 .pending = uartlite_serial_pending,
121 .getc = uartlite_serial_getc,
122};
Michal Simekd40a2522012-07-02 10:32:18 +0200123
Michal Simek7e4372a2015-12-01 14:24:20 +0100124static const struct udevice_id uartlite_serial_ids[] = {
125 { .compatible = "xlnx,opb-uartlite-1.00.b", },
126 { .compatible = "xlnx,xps-uartlite-1.00.a" },
127 { }
128};
Marek Vasutd97fb5c2012-09-12 19:45:58 +0200129
Michal Simek7e4372a2015-12-01 14:24:20 +0100130U_BOOT_DRIVER(serial_uartlite) = {
131 .name = "serial_uartlite",
132 .id = UCLASS_SERIAL,
133 .of_match = uartlite_serial_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700134 .of_to_plat = uartlite_serial_of_to_plat,
Simon Glassb75b15b2020-12-03 16:55:23 -0700135 .plat_auto = sizeof(struct uartlite_plat),
Michal Simek7e4372a2015-12-01 14:24:20 +0100136 .probe = uartlite_serial_probe,
137 .ops = &uartlite_serial_ops,
Michal Simek7e4372a2015-12-01 14:24:20 +0100138};
Michal Simek8af618b2015-12-14 16:55:10 +0100139
140#ifdef CONFIG_DEBUG_UART_UARTLITE
141
142#include <debug_uart.h>
143
144static inline void _debug_uart_init(void)
145{
Pali Rohár8864b352022-05-27 22:15:24 +0200146 struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE);
T Karthik Reddy070ffd22020-08-14 03:02:15 -0600147 int ret;
Michal Simek8af618b2015-12-14 16:55:10 +0100148
T Karthik Reddy070ffd22020-08-14 03:02:15 -0600149 uart_out32(&regs->control, 0);
150 uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
Ashok Reddy Soma5190dec2020-12-01 00:34:47 -0700151 ret = uart_in32(&regs->status);
T Karthik Reddy070ffd22020-08-14 03:02:15 -0600152 /* Endianness detection */
153 if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
154 little_endian = true;
155 uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
156 ULITE_CONTROL_RST_TX);
157 }
Michal Simek8af618b2015-12-14 16:55:10 +0100158}
159
160static inline void _debug_uart_putc(int ch)
161{
Pali Rohár8864b352022-05-27 22:15:24 +0200162 struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE);
Michal Simek8af618b2015-12-14 16:55:10 +0100163
T Karthik Reddy070ffd22020-08-14 03:02:15 -0600164 while (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
Michal Simek8af618b2015-12-14 16:55:10 +0100165 ;
166
T Karthik Reddy070ffd22020-08-14 03:02:15 -0600167 uart_out32(&regs->tx_fifo, ch & 0xff);
Michal Simek8af618b2015-12-14 16:55:10 +0100168}
169
170DEBUG_UART_FUNCS
171#endif