Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2016 Rockchip Electronics Co., Ltd |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 7 | #include <init.h> |
Kever Yang | b04029e | 2019-07-22 19:59:33 +0800 | [diff] [blame] | 8 | #include <asm/arch-rockchip/bootrom.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 9 | #include <asm/arch-rockchip/hardware.h> |
Kever Yang | 5a9a2aa | 2019-07-22 20:01:58 +0800 | [diff] [blame] | 10 | #include <asm/arch-rockchip/grf_rk3328.h> |
| 11 | #include <asm/arch-rockchip/uart.h> |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 12 | #include <asm/armv8/mmu.h> |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 13 | |
Kever Yang | 5a9a2aa | 2019-07-22 20:01:58 +0800 | [diff] [blame] | 14 | #define CRU_BASE 0xFF440000 |
| 15 | #define GRF_BASE 0xFF100000 |
| 16 | #define UART2_BASE 0xFF130000 |
Kever Yang | a18a645 | 2019-07-29 12:18:18 +0300 | [diff] [blame] | 17 | #define FW_DDR_CON_REG 0xFF7C0040 |
Jonas Karlman | cac3311 | 2024-01-07 18:18:33 +0000 | [diff] [blame] | 18 | #define EFUSE_NS_BASE 0xFF260000 |
| 19 | |
| 20 | #define EFUSE_MOD 0x0000 |
| 21 | #define EFUSE_INT_CON 0x0014 |
| 22 | #define EFUSE_T_CSB_P 0x0028 |
| 23 | #define EFUSE_T_PGENB_P 0x002C |
| 24 | #define EFUSE_T_LOAD_P 0x0030 |
| 25 | #define EFUSE_T_ADDR_P 0x0034 |
| 26 | #define EFUSE_T_STROBE_P 0x0038 |
| 27 | #define EFUSE_T_CSB_R 0x003C |
| 28 | #define EFUSE_T_PGENB_R 0x0040 |
| 29 | #define EFUSE_T_LOAD_R 0x0044 |
| 30 | #define EFUSE_T_ADDR_R 0x0048 |
| 31 | #define EFUSE_T_STROBE_R 0x004C |
| 32 | |
| 33 | #define EFUSE_USER_MODE 0x1 |
| 34 | #define EFUSE_TIMING(s, l) (((s) << 16) | (l)) |
Kever Yang | 5a9a2aa | 2019-07-22 20:01:58 +0800 | [diff] [blame] | 35 | |
Kever Yang | b04029e | 2019-07-22 19:59:33 +0800 | [diff] [blame] | 36 | const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { |
Johan Jonker | f05aa9d | 2022-04-15 23:21:43 +0200 | [diff] [blame] | 37 | [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000", |
Jonas Karlman | e4b50e0 | 2024-02-17 00:22:39 +0000 | [diff] [blame] | 38 | [BROM_BOOTSOURCE_SPINOR] = "/spi@ff190000/flash@0", |
Johan Jonker | f05aa9d | 2022-04-15 23:21:43 +0200 | [diff] [blame] | 39 | [BROM_BOOTSOURCE_SD] = "/mmc@ff500000", |
Kever Yang | b04029e | 2019-07-22 19:59:33 +0800 | [diff] [blame] | 40 | }; |
| 41 | |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 42 | static struct mm_region rk3328_mem_map[] = { |
| 43 | { |
| 44 | .virt = 0x0UL, |
| 45 | .phys = 0x0UL, |
Kever Yang | 6cd0cab | 2017-06-13 21:00:12 +0800 | [diff] [blame] | 46 | .size = 0xff000000UL, |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 47 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 48 | PTE_BLOCK_INNER_SHARE |
| 49 | }, { |
Kever Yang | 6cd0cab | 2017-06-13 21:00:12 +0800 | [diff] [blame] | 50 | .virt = 0xff000000UL, |
| 51 | .phys = 0xff000000UL, |
| 52 | .size = 0x1000000UL, |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 53 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 54 | PTE_BLOCK_NON_SHARE | |
| 55 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 56 | }, { |
| 57 | /* List terminator */ |
| 58 | 0, |
| 59 | } |
| 60 | }; |
| 61 | |
| 62 | struct mm_region *mem_map = rk3328_mem_map; |
| 63 | |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 64 | int arch_cpu_init(void) |
| 65 | { |
Kever Yang | a18a645 | 2019-07-29 12:18:18 +0300 | [diff] [blame] | 66 | #ifdef CONFIG_SPL_BUILD |
Jonas Karlman | cac3311 | 2024-01-07 18:18:33 +0000 | [diff] [blame] | 67 | u32 reg; |
| 68 | |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 69 | /* We do some SoC one time setting here. */ |
| 70 | |
Kever Yang | a18a645 | 2019-07-29 12:18:18 +0300 | [diff] [blame] | 71 | /* Disable the ddr secure region setting to make it non-secure */ |
| 72 | rk_setreg(FW_DDR_CON_REG, 0x200); |
Jonas Karlman | cac3311 | 2024-01-07 18:18:33 +0000 | [diff] [blame] | 73 | |
| 74 | /* Use efuse auto mode */ |
| 75 | reg = readl(EFUSE_NS_BASE + EFUSE_MOD); |
| 76 | writel(reg & ~EFUSE_USER_MODE, EFUSE_NS_BASE + EFUSE_MOD); |
| 77 | |
| 78 | /* Enable efuse finish and auto access err interrupt */ |
| 79 | writel(0x07, EFUSE_NS_BASE + EFUSE_INT_CON); |
| 80 | |
| 81 | /* Set efuse timing control */ |
| 82 | writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_CSB_P); |
| 83 | writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_PGENB_P); |
| 84 | writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_LOAD_P); |
| 85 | writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_ADDR_P); |
| 86 | writel(EFUSE_TIMING(2, 240), EFUSE_NS_BASE + EFUSE_T_STROBE_P); |
| 87 | writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_CSB_R); |
| 88 | writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_PGENB_R); |
| 89 | writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_LOAD_R); |
| 90 | writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_ADDR_R); |
| 91 | writel(EFUSE_TIMING(2, 3), EFUSE_NS_BASE + EFUSE_T_STROBE_R); |
Kever Yang | a18a645 | 2019-07-29 12:18:18 +0300 | [diff] [blame] | 92 | #endif |
Kever Yang | ec02b3c | 2017-02-23 15:37:51 +0800 | [diff] [blame] | 93 | return 0; |
| 94 | } |
Kever Yang | 5a9a2aa | 2019-07-22 20:01:58 +0800 | [diff] [blame] | 95 | |
| 96 | void board_debug_uart_init(void) |
| 97 | { |
| 98 | struct rk3328_grf_regs * const grf = (void *)GRF_BASE; |
| 99 | struct rk_uart * const uart = (void *)UART2_BASE; |
| 100 | enum{ |
| 101 | GPIO2A0_SEL_SHIFT = 0, |
| 102 | GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, |
| 103 | GPIO2A0_UART2_TX_M1 = 1, |
| 104 | |
| 105 | GPIO2A1_SEL_SHIFT = 2, |
| 106 | GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, |
| 107 | GPIO2A1_UART2_RX_M1 = 1, |
| 108 | }; |
| 109 | enum { |
| 110 | IOMUX_SEL_UART2_SHIFT = 0, |
| 111 | IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, |
| 112 | IOMUX_SEL_UART2_M0 = 0, |
| 113 | IOMUX_SEL_UART2_M1, |
| 114 | }; |
| 115 | |
| 116 | /* uart_sel_clk default select 24MHz */ |
| 117 | writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148); |
| 118 | |
| 119 | /* init uart baud rate 1500000 */ |
| 120 | writel(0x83, &uart->lcr); |
| 121 | writel(0x1, &uart->rbr); |
| 122 | writel(0x3, &uart->lcr); |
| 123 | |
| 124 | /* Enable early UART2 */ |
| 125 | rk_clrsetreg(&grf->com_iomux, |
| 126 | IOMUX_SEL_UART2_MASK, |
| 127 | IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT); |
| 128 | rk_clrsetreg(&grf->gpio2a_iomux, |
| 129 | GPIO2A0_SEL_MASK, |
| 130 | GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT); |
| 131 | rk_clrsetreg(&grf->gpio2a_iomux, |
| 132 | GPIO2A1_SEL_MASK, |
| 133 | GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT); |
| 134 | |
| 135 | /* enable FIFO */ |
| 136 | writel(0x1, &uart->sfe); |
| 137 | } |