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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutc140e982011-11-08 23:18:08 +00002/*
Otavio Salvadorfd96c032013-01-11 03:19:08 +00003 * Freescale i.MX23/i.MX28 common code
Marek Vasutc140e982011-11-08 23:18:08 +00004 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
7 *
8 * Based on code from LTIB:
9 * Copyright (C) 2010 Freescale Semiconductor, Inc.
Marek Vasutc140e982011-11-08 23:18:08 +000010 */
11
12#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -060013#include <command.h>
Simon Glassafb02152019-12-28 10:45:01 -070014#include <cpu_func.h>
Simon Glassf11478f2019-12-28 10:45:07 -070015#include <hang.h>
Simon Glass97589732020-05-10 11:40:02 -060016#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060017#include <net.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060018#include <asm/global_data.h>
Simon Glassdbd79542020-05-10 11:40:11 -060019#include <linux/delay.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090020#include <linux/errno.h>
Marek Vasutc140e982011-11-08 23:18:08 +000021#include <asm/io.h>
22#include <asm/arch/clock.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020023#include <asm/mach-imx/dma.h>
Marek Vasutc140e982011-11-08 23:18:08 +000024#include <asm/arch/gpio.h>
Marek Vasut53fdab22011-11-08 23:18:13 +000025#include <asm/arch/iomux.h>
Marek Vasutc140e982011-11-08 23:18:08 +000026#include <asm/arch/imx-regs.h>
27#include <asm/arch/sys_proto.h>
Marek BehĂșn90dcc4f2021-05-20 13:24:12 +020028#include <asm/sections.h>
Fabio Estevam570dcfd2013-01-08 05:21:45 +000029#include <linux/compiler.h>
Marek Vasutc140e982011-11-08 23:18:08 +000030
Marek Vasut5bf48fb2011-11-08 23:18:23 +000031DECLARE_GLOBAL_DATA_PTR;
32
Marek Vasutc140e982011-11-08 23:18:08 +000033/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
Mans Rullgard04ef8652018-04-21 16:11:06 +010034__weak void lowlevel_init(void) {}
Marek Vasutc140e982011-11-08 23:18:08 +000035
Harald Seiler6f14d5f2020-12-15 16:47:52 +010036void reset_cpu(void) __attribute__((noreturn));
Marek Vasutc140e982011-11-08 23:18:08 +000037
Harald Seiler6f14d5f2020-12-15 16:47:52 +010038void reset_cpu(void)
Marek Vasutc140e982011-11-08 23:18:08 +000039{
Otavio Salvador22f4ff92012-08-05 09:05:31 +000040 struct mxs_rtc_regs *rtc_regs =
41 (struct mxs_rtc_regs *)MXS_RTC_BASE;
42 struct mxs_lcdif_regs *lcdif_regs =
43 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
Marek Vasut9c53b7e2012-05-01 11:09:47 +000044
45 /*
46 * Shut down the LCD controller as it interferes with BootROM boot mode
47 * pads sampling.
48 */
49 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
Marek Vasutc140e982011-11-08 23:18:08 +000050
51 /* Wait 1 uS before doing the actual watchdog reset */
52 writel(1, &rtc_regs->hw_rtc_watchdog);
53 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
54
55 /* Endless loop, reset will exit from here */
56 for (;;)
57 ;
58}
59
Marek Vasut39c31032013-04-25 16:37:12 +000060/*
61 * This function will craft a jumptable at 0x0 which will redirect interrupt
62 * vectoring to proper location of U-Boot in RAM.
63 *
64 * The structure of the jumptable will be as follows:
65 * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
66 * <destination address> ... for each previous ldr, thus also repeated 8 times
67 *
68 * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
69 * offset 0x18 from current value of PC register. Note that PC is already
70 * incremented by 4 when computing the offset, so the effective offset is
71 * actually 0x20, this the associated <destination address>. Loading the PC
72 * register with an address performs a jump to that address.
73 */
Marek Vasutd1937632023-10-18 20:51:59 +020074noinline __attribute__((target("arm")))
Marek Vasut5bf48fb2011-11-08 23:18:23 +000075void mx28_fixup_vt(uint32_t start_addr)
76{
Marek Vasut39c31032013-04-25 16:37:12 +000077 /* ldr pc, [pc, #0x18] */
78 const uint32_t ldr_pc = 0xe59ff018;
79 /* Jumptable location is 0x0 */
80 uint32_t *vt = (uint32_t *)0x0;
Marek Vasut5bf48fb2011-11-08 23:18:23 +000081 int i;
82
Marek Vasut39c31032013-04-25 16:37:12 +000083 for (i = 0; i < 8; i++) {
Wolfgang Denk6ae80832014-11-06 14:02:57 +010084 /* cppcheck-suppress nullPointer */
Marek Vasut39c31032013-04-25 16:37:12 +000085 vt[i] = ldr_pc;
Wolfgang Denk6ae80832014-11-06 14:02:57 +010086 /* cppcheck-suppress nullPointer */
Marek Vasut39c31032013-04-25 16:37:12 +000087 vt[i + 8] = start_addr + (4 * i);
88 }
Marek Vasutd1937632023-10-18 20:51:59 +020089
90 /* Make sure ARM core points to low vectors */
91 set_cr(get_cr() & ~CR_V);
Marek Vasut5bf48fb2011-11-08 23:18:23 +000092}
93
94#ifdef CONFIG_ARCH_MISC_INIT
95int arch_misc_init(void)
96{
97 mx28_fixup_vt(gd->relocaddr);
Marek Vasutc140e982011-11-08 23:18:08 +000098 return 0;
99}
Marek Vasut5bf48fb2011-11-08 23:18:23 +0000100#endif
Marek Vasutc140e982011-11-08 23:18:08 +0000101
Marek Vasutc140e982011-11-08 23:18:08 +0000102int arch_cpu_init(void)
103{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000104 struct mxs_clkctrl_regs *clkctrl_regs =
105 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasut5bf48fb2011-11-08 23:18:23 +0000106
Shiji Yangeff11fa2023-08-03 09:47:17 +0800107 mx28_fixup_vt((uint32_t)_start);
Marek Vasutc140e982011-11-08 23:18:08 +0000108
109 /*
110 * Enable NAND clock
111 */
Rasmus Villemoes6cb658c2019-09-12 09:17:10 +0000112 /* Set bypass bit */
Marek Vasutc140e982011-11-08 23:18:08 +0000113 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
114 &clkctrl_regs->hw_clkctrl_clkseq_set);
115
Rasmus Villemoes6cb658c2019-09-12 09:17:10 +0000116 /* Set GPMI clock to ref_xtal / 1 */
Rasmus Villemoes5a84b032019-09-12 09:17:11 +0000117 clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
118 while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
119 ;
Marek Vasutc140e982011-11-08 23:18:08 +0000120 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
Rasmus Villemoes5a84b032019-09-12 09:17:11 +0000121 CLKCTRL_GPMI_DIV_MASK, 1);
Marek Vasutc140e982011-11-08 23:18:08 +0000122
123 udelay(1000);
124
Marek Vasut53fdab22011-11-08 23:18:13 +0000125 /*
126 * Configure GPIO unit
127 */
128 mxs_gpio_init();
129
Marek Vasut93541b42012-04-08 17:34:46 +0000130#ifdef CONFIG_APBH_DMA
131 /* Start APBH DMA */
132 mxs_dma_init();
133#endif
134
Marek Vasutc140e982011-11-08 23:18:08 +0000135 return 0;
136}
Marek Vasutc140e982011-11-08 23:18:08 +0000137
Peng Fanb741b162015-08-13 10:55:33 +0800138u32 get_cpu_rev(void)
Otavio Salvadorca36b532012-07-28 11:43:47 +0000139{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000140 struct mxs_digctl_regs *digctl_regs =
141 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
Otavio Salvadorca36b532012-07-28 11:43:47 +0000142 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
143
144 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
Otavio Salvadorfd96c032013-01-11 03:19:08 +0000145 case HW_DIGCTL_CHIPID_MX23:
146 switch (rev) {
147 case 0x0:
Otavio Salvadorfd96c032013-01-11 03:19:08 +0000148 case 0x1:
Otavio Salvadorfd96c032013-01-11 03:19:08 +0000149 case 0x2:
Otavio Salvadorfd96c032013-01-11 03:19:08 +0000150 case 0x3:
Otavio Salvadorfd96c032013-01-11 03:19:08 +0000151 case 0x4:
Peng Fanb741b162015-08-13 10:55:33 +0800152 return (MXC_CPU_MX23 << 12) | (rev + 0x10);
Otavio Salvadorfd96c032013-01-11 03:19:08 +0000153 default:
Peng Fanb741b162015-08-13 10:55:33 +0800154 return 0;
Otavio Salvadorfd96c032013-01-11 03:19:08 +0000155 }
Otavio Salvadorca36b532012-07-28 11:43:47 +0000156 case HW_DIGCTL_CHIPID_MX28:
157 switch (rev) {
158 case 0x1:
Peng Fanb741b162015-08-13 10:55:33 +0800159 return (MXC_CPU_MX28 << 12) | 0x12;
Otavio Salvadorca36b532012-07-28 11:43:47 +0000160 default:
Peng Fanb741b162015-08-13 10:55:33 +0800161 return 0;
Otavio Salvadorca36b532012-07-28 11:43:47 +0000162 }
163 default:
Peng Fanb741b162015-08-13 10:55:33 +0800164 return 0;
165 }
166}
167
168#if defined(CONFIG_DISPLAY_CPUINFO)
169const char *get_imx_type(u32 imxtype)
170{
171 switch (imxtype) {
172 case MXC_CPU_MX23:
Michael Heimpold0ad9e1f2016-06-06 14:26:39 +0200173 return "23";
Peng Fanb741b162015-08-13 10:55:33 +0800174 case MXC_CPU_MX28:
Michael Heimpold0ad9e1f2016-06-06 14:26:39 +0200175 return "28";
Peng Fanb741b162015-08-13 10:55:33 +0800176 default:
Otavio Salvadorca36b532012-07-28 11:43:47 +0000177 return "??";
178 }
179}
180
Marek Vasutc140e982011-11-08 23:18:08 +0000181int print_cpuinfo(void)
182{
Peng Fanb741b162015-08-13 10:55:33 +0800183 u32 cpurev;
Mans Rullgard2f66b402018-04-21 16:11:09 +0100184 struct mxs_spl_data *data = MXS_SPL_DATA;
Marek Vasutb28fe462012-05-01 11:09:45 +0000185
Peng Fanb741b162015-08-13 10:55:33 +0800186 cpurev = get_cpu_rev();
187 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
188 get_imx_type((cpurev & 0xFF000) >> 12),
189 (cpurev & 0x000F0) >> 4,
190 (cpurev & 0x0000F) >> 0,
Otavio Salvadorca36b532012-07-28 11:43:47 +0000191 mxc_get_clock(MXC_ARM_CLK) / 1000000);
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000192 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
Marek Vasutc140e982011-11-08 23:18:08 +0000193 return 0;
194}
195#endif
196
Simon Glassed38aef2020-05-10 11:40:03 -0600197int do_mx28_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
198 char *const argv[])
Marek Vasutc140e982011-11-08 23:18:08 +0000199{
200 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
201 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
202 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
203 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
204 return 0;
205}
206
207/*
208 * Initializes on-chip ethernet controllers.
209 */
Otavio Salvadord1de2e02012-08-19 04:58:29 +0000210#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900211int cpu_eth_init(struct bd_info *bis)
Marek Vasutc140e982011-11-08 23:18:08 +0000212{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000213 struct mxs_clkctrl_regs *clkctrl_regs =
214 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasutc140e982011-11-08 23:18:08 +0000215
216 /* Turn on ENET clocks */
217 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
218 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
219
220 /* Set up ENET PLL for 50 MHz */
221 /* Power on ENET PLL */
222 writel(CLKCTRL_PLL2CTRL0_POWER,
223 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
224
225 udelay(10);
226
227 /* Gate on ENET PLL */
228 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
229 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
230
231 /* Enable pad output */
232 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
233
234 return 0;
235}
236#endif
237
Fabio Estevam570dcfd2013-01-08 05:21:45 +0000238__weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
Fabio Estevam4029c012011-12-20 06:42:29 +0000239{
240 mac[0] = 0x00;
241 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
242
243 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
244 mac[5] += 1;
245}
246
Fabio Estevam4029c012011-12-20 06:42:29 +0000247#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
248
249#define MXS_OCOTP_MAX_TIMEOUT 1000000
250void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
251{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000252 struct mxs_ocotp_regs *ocotp_regs =
253 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
Fabio Estevam4029c012011-12-20 06:42:29 +0000254 uint32_t data;
255
256 memset(mac, 0, 6);
257
258 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
259
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000260 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
Fabio Estevam4029c012011-12-20 06:42:29 +0000261 MXS_OCOTP_MAX_TIMEOUT)) {
262 printf("MXS FEC: Can't get MAC from OCOTP\n");
263 return;
264 }
265
266 data = readl(&ocotp_regs->hw_ocotp_cust0);
267
268 mac[2] = (data >> 24) & 0xff;
269 mac[3] = (data >> 16) & 0xff;
270 mac[4] = (data >> 8) & 0xff;
271 mac[5] = data & 0xff;
272 mx28_adjust_mac(dev_id, mac);
273}
274#else
275void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
276{
277 memset(mac, 0, 6);
278}
279#endif
280
Otavio Salvadora2bbe0c2012-08-19 04:58:30 +0000281int mxs_dram_init(void)
Fabio Estevam93f3a892011-12-20 05:46:33 +0000282{
Mans Rullgard2f66b402018-04-21 16:11:09 +0100283 struct mxs_spl_data *data = MXS_SPL_DATA;
Fabio Estevam93f3a892011-12-20 05:46:33 +0000284
Marek Vasut9136fe92012-05-01 11:09:44 +0000285 if (data->mem_dram_size == 0) {
Otavio Salvadora2bbe0c2012-08-19 04:58:30 +0000286 printf("MXS:\n"
Marek Vasut9136fe92012-05-01 11:09:44 +0000287 "Error, the RAM size passed up from SPL is 0!\n");
Fabio Estevam93f3a892011-12-20 05:46:33 +0000288 hang();
289 }
290
Marek Vasut9136fe92012-05-01 11:09:44 +0000291 gd->ram_size = data->mem_dram_size;
Fabio Estevam93f3a892011-12-20 05:46:33 +0000292 return 0;
293}
294
Marek Vasutc140e982011-11-08 23:18:08 +0000295U_BOOT_CMD(
296 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
297 "display clocks",
298 ""
299);