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Marek Vasutc140e982011-11-08 23:18:08 +00001/*
2 * Freescale i.MX28 common code
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <asm/errno.h>
31#include <asm/io.h>
32#include <asm/arch/clock.h>
Marek Vasut93541b42012-04-08 17:34:46 +000033#include <asm/arch/dma.h>
Marek Vasutc140e982011-11-08 23:18:08 +000034#include <asm/arch/gpio.h>
Marek Vasut53fdab22011-11-08 23:18:13 +000035#include <asm/arch/iomux.h>
Marek Vasutc140e982011-11-08 23:18:08 +000036#include <asm/arch/imx-regs.h>
37#include <asm/arch/sys_proto.h>
38
Marek Vasut5bf48fb2011-11-08 23:18:23 +000039DECLARE_GLOBAL_DATA_PTR;
40
Marek Vasutc140e982011-11-08 23:18:08 +000041/* 1 second delay should be plenty of time for block reset. */
42#define RESET_MAX_TIMEOUT 1000000
43
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +000044#define MXS_BLOCK_SFTRST (1 << 31)
45#define MXS_BLOCK_CLKGATE (1 << 30)
Marek Vasutc140e982011-11-08 23:18:08 +000046
47/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
48inline void lowlevel_init(void) {}
49
50void reset_cpu(ulong ignored) __attribute__((noreturn));
51
52void reset_cpu(ulong ignored)
53{
Otavio Salvador22f4ff92012-08-05 09:05:31 +000054 struct mxs_rtc_regs *rtc_regs =
55 (struct mxs_rtc_regs *)MXS_RTC_BASE;
56 struct mxs_lcdif_regs *lcdif_regs =
57 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
Marek Vasut9c53b7e2012-05-01 11:09:47 +000058
59 /*
60 * Shut down the LCD controller as it interferes with BootROM boot mode
61 * pads sampling.
62 */
63 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
Marek Vasutc140e982011-11-08 23:18:08 +000064
65 /* Wait 1 uS before doing the actual watchdog reset */
66 writel(1, &rtc_regs->hw_rtc_watchdog);
67 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
68
69 /* Endless loop, reset will exit from here */
70 for (;;)
71 ;
72}
73
Marek Vasut6e5ce312012-03-15 18:33:23 +000074void enable_caches(void)
75{
76#ifndef CONFIG_SYS_ICACHE_OFF
77 icache_enable();
78#endif
79#ifndef CONFIG_SYS_DCACHE_OFF
80 dcache_enable();
81#endif
82}
83
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +000084int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
Marek Vasutc140e982011-11-08 23:18:08 +000085{
86 while (--timeout) {
87 if ((readl(&reg->reg) & mask) == mask)
88 break;
89 udelay(1);
90 }
91
92 return !timeout;
93}
94
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +000095int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
Marek Vasutc140e982011-11-08 23:18:08 +000096{
97 while (--timeout) {
98 if ((readl(&reg->reg) & mask) == 0)
99 break;
100 udelay(1);
101 }
102
103 return !timeout;
104}
105
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000106int mxs_reset_block(struct mxs_register_32 *reg)
Marek Vasutc140e982011-11-08 23:18:08 +0000107{
108 /* Clear SFTRST */
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000109 writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
Marek Vasutc140e982011-11-08 23:18:08 +0000110
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000111 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
Marek Vasutc140e982011-11-08 23:18:08 +0000112 return 1;
113
114 /* Clear CLKGATE */
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000115 writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
Marek Vasutc140e982011-11-08 23:18:08 +0000116
117 /* Set SFTRST */
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000118 writel(MXS_BLOCK_SFTRST, &reg->reg_set);
Marek Vasutc140e982011-11-08 23:18:08 +0000119
120 /* Wait for CLKGATE being set */
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000121 if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
Marek Vasutc140e982011-11-08 23:18:08 +0000122 return 1;
123
124 /* Clear SFTRST */
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000125 writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
Marek Vasutc140e982011-11-08 23:18:08 +0000126
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000127 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
Marek Vasutc140e982011-11-08 23:18:08 +0000128 return 1;
129
130 /* Clear CLKGATE */
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000131 writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
Marek Vasutc140e982011-11-08 23:18:08 +0000132
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000133 if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
Marek Vasutc140e982011-11-08 23:18:08 +0000134 return 1;
135
Marek Vasut5bf48fb2011-11-08 23:18:23 +0000136 return 0;
137}
138
139void mx28_fixup_vt(uint32_t start_addr)
140{
141 uint32_t *vt = (uint32_t *)0x20;
142 int i;
143
144 for (i = 0; i < 8; i++)
145 vt[i] = start_addr + (4 * i);
146}
147
148#ifdef CONFIG_ARCH_MISC_INIT
149int arch_misc_init(void)
150{
151 mx28_fixup_vt(gd->relocaddr);
Marek Vasutc140e982011-11-08 23:18:08 +0000152 return 0;
153}
Marek Vasut5bf48fb2011-11-08 23:18:23 +0000154#endif
Marek Vasutc140e982011-11-08 23:18:08 +0000155
Marek Vasutc140e982011-11-08 23:18:08 +0000156int arch_cpu_init(void)
157{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000158 struct mxs_clkctrl_regs *clkctrl_regs =
159 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasut5bf48fb2011-11-08 23:18:23 +0000160 extern uint32_t _start;
161
162 mx28_fixup_vt((uint32_t)&_start);
Marek Vasutc140e982011-11-08 23:18:08 +0000163
164 /*
165 * Enable NAND clock
166 */
167 /* Clear bypass bit */
168 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
169 &clkctrl_regs->hw_clkctrl_clkseq_set);
170
171 /* Set GPMI clock to ref_gpmi / 12 */
172 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
173 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
174
175 udelay(1000);
176
Marek Vasut53fdab22011-11-08 23:18:13 +0000177 /*
178 * Configure GPIO unit
179 */
180 mxs_gpio_init();
181
Marek Vasut93541b42012-04-08 17:34:46 +0000182#ifdef CONFIG_APBH_DMA
183 /* Start APBH DMA */
184 mxs_dma_init();
185#endif
186
Marek Vasutc140e982011-11-08 23:18:08 +0000187 return 0;
188}
Marek Vasutc140e982011-11-08 23:18:08 +0000189
190#if defined(CONFIG_DISPLAY_CPUINFO)
Otavio Salvadorca36b532012-07-28 11:43:47 +0000191static const char *get_cpu_type(void)
192{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000193 struct mxs_digctl_regs *digctl_regs =
194 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
Otavio Salvadorca36b532012-07-28 11:43:47 +0000195
196 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
197 case HW_DIGCTL_CHIPID_MX28:
198 return "28";
199 default:
200 return "??";
201 }
202}
203
204static const char *get_cpu_rev(void)
205{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000206 struct mxs_digctl_regs *digctl_regs =
207 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
Otavio Salvadorca36b532012-07-28 11:43:47 +0000208 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
209
210 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
211 case HW_DIGCTL_CHIPID_MX28:
212 switch (rev) {
213 case 0x1:
214 return "1.2";
215 default:
216 return "??";
217 }
218 default:
219 return "??";
220 }
221}
222
Marek Vasutc140e982011-11-08 23:18:08 +0000223int print_cpuinfo(void)
224{
Otavio Salvadorf930ea62012-08-05 09:05:32 +0000225 struct mxs_spl_data *data = (struct mxs_spl_data *)
226 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
Marek Vasutb28fe462012-05-01 11:09:45 +0000227
Otavio Salvadorca36b532012-07-28 11:43:47 +0000228 printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
229 get_cpu_type(),
230 get_cpu_rev(),
231 mxc_get_clock(MXC_ARM_CLK) / 1000000);
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000232 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
Marek Vasutc140e982011-11-08 23:18:08 +0000233 return 0;
234}
235#endif
236
237int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
238{
239 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
240 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
241 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
242 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
243 return 0;
244}
245
246/*
247 * Initializes on-chip ethernet controllers.
248 */
Otavio Salvadord1de2e02012-08-19 04:58:29 +0000249#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
Marek Vasutc140e982011-11-08 23:18:08 +0000250int cpu_eth_init(bd_t *bis)
251{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000252 struct mxs_clkctrl_regs *clkctrl_regs =
253 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasutc140e982011-11-08 23:18:08 +0000254
255 /* Turn on ENET clocks */
256 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
257 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
258
259 /* Set up ENET PLL for 50 MHz */
260 /* Power on ENET PLL */
261 writel(CLKCTRL_PLL2CTRL0_POWER,
262 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
263
264 udelay(10);
265
266 /* Gate on ENET PLL */
267 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
268 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
269
270 /* Enable pad output */
271 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
272
273 return 0;
274}
275#endif
276
Fabio Estevam4029c012011-12-20 06:42:29 +0000277static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
278{
279 mac[0] = 0x00;
280 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
281
282 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
283 mac[5] += 1;
284}
285
286void mx28_adjust_mac(int dev_id, unsigned char *mac)
287 __attribute__((weak, alias("__mx28_adjust_mac")));
288
289#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
290
291#define MXS_OCOTP_MAX_TIMEOUT 1000000
292void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
293{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000294 struct mxs_ocotp_regs *ocotp_regs =
295 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
Fabio Estevam4029c012011-12-20 06:42:29 +0000296 uint32_t data;
297
298 memset(mac, 0, 6);
299
300 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
301
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000302 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
Fabio Estevam4029c012011-12-20 06:42:29 +0000303 MXS_OCOTP_MAX_TIMEOUT)) {
304 printf("MXS FEC: Can't get MAC from OCOTP\n");
305 return;
306 }
307
308 data = readl(&ocotp_regs->hw_ocotp_cust0);
309
310 mac[2] = (data >> 24) & 0xff;
311 mac[3] = (data >> 16) & 0xff;
312 mac[4] = (data >> 8) & 0xff;
313 mac[5] = data & 0xff;
314 mx28_adjust_mac(dev_id, mac);
315}
316#else
317void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
318{
319 memset(mac, 0, 6);
320}
321#endif
322
Otavio Salvadora2bbe0c2012-08-19 04:58:30 +0000323int mxs_dram_init(void)
Fabio Estevam93f3a892011-12-20 05:46:33 +0000324{
Otavio Salvadorf930ea62012-08-05 09:05:32 +0000325 struct mxs_spl_data *data = (struct mxs_spl_data *)
326 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
Fabio Estevam93f3a892011-12-20 05:46:33 +0000327
Marek Vasut9136fe92012-05-01 11:09:44 +0000328 if (data->mem_dram_size == 0) {
Otavio Salvadora2bbe0c2012-08-19 04:58:30 +0000329 printf("MXS:\n"
Marek Vasut9136fe92012-05-01 11:09:44 +0000330 "Error, the RAM size passed up from SPL is 0!\n");
Fabio Estevam93f3a892011-12-20 05:46:33 +0000331 hang();
332 }
333
Marek Vasut9136fe92012-05-01 11:09:44 +0000334 gd->ram_size = data->mem_dram_size;
Fabio Estevam93f3a892011-12-20 05:46:33 +0000335 return 0;
336}
337
Marek Vasutc140e982011-11-08 23:18:08 +0000338U_BOOT_CMD(
339 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
340 "display clocks",
341 ""
342);