blob: 9ab98d4b686cafdd213ebf1ced8cd3f475513b2d [file] [log] [blame]
wdenk0aeb8532004-10-10 21:21:55 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk0aeb8532004-10-10 21:21:55 +000025#include <common.h>
26#include <pci.h>
27#include <asm/processor.h>
28#include <asm/immap_85xx.h>
Wolfgang Denkcd0bf802005-07-21 16:14:36 +020029#include <ioports.h>
wdenk0aeb8532004-10-10 21:21:55 +000030#include <spd.h>
Kumar Galad28ced32007-11-29 00:11:44 -060031#include <libfdt.h>
32#include <fdt_support.h>
wdenk0aeb8532004-10-10 21:21:55 +000033
34#include "../common/cadmus.h"
35#include "../common/eeprom.h"
Matthew McClintock3b662012006-06-28 10:46:13 -050036#include "../common/via.h"
wdenk0aeb8532004-10-10 21:21:55 +000037
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050038#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk0aeb8532004-10-10 21:21:55 +000039extern void ddr_enable_ecc(unsigned int dram_size);
40#endif
41
42extern long int spd_sdram(void);
43
44void local_bus_init(void);
45void sdram_init(void);
46
Wolfgang Denkcd0bf802005-07-21 16:14:36 +020047/*
48 * I/O Port configuration table
49 *
50 * if conf is 1, then that port pin will be configured at boot time
51 * according to the five values podr/pdir/ppar/psor/pdat for that entry
52 */
53
54const iop_conf_t iop_conf_tab[4][32] = {
55
56 /* Port A configuration */
57 { /* conf ppar psor pdir podr pdat */
58 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
59 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
60 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
61 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
62 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
63 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
64 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
65 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
66 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
67 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
68 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
69 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
70 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
71 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
72 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
73 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
74 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
75 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
76 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
77 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
78 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
79 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
80 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
81 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
82 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
83 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
84 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
85 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
86 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
87 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
88 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
89 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
90 },
91
92 /* Port B configuration */
93 { /* conf ppar psor pdir podr pdat */
94 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
95 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
96 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
97 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
98 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
99 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
100 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
101 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
102 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
103 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
104 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
105 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
106 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
107 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
108 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
109 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
110 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
111 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
112 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
113 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
114 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
117 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
118 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
121 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
122 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
124 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
125 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
126 },
127
128 /* Port C */
129 { /* conf ppar psor pdir podr pdat */
130 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
131 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
132 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
133 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
134 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
135 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
136 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
137 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
138 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
139 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
140 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
141 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
142 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
143 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
144 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
145 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
146 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
147 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
148 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
149 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
150 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
151 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
152 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
153 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
154 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
155 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
156 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
157 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
158 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
159 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
160 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
161 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
162 },
163
164 /* Port D */
165 { /* conf ppar psor pdir podr pdat */
166 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
167 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
168 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
169 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
170 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
171 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
172 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
173 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
174 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
175 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
176 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
177 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
178 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
179 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
180 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
181 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
182 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
183 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
184 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
185 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
186 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
187 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
188 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
189 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
190 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
191 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
192 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
193 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
194 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
196 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
197 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
198 }
199};
200
wdenkef3386f2004-10-10 21:27:30 +0000201int board_early_init_f (void)
wdenk0aeb8532004-10-10 21:21:55 +0000202{
wdenkef3386f2004-10-10 21:27:30 +0000203 return 0;
wdenk0aeb8532004-10-10 21:21:55 +0000204}
205
wdenkef3386f2004-10-10 21:27:30 +0000206int checkboard (void)
wdenk0aeb8532004-10-10 21:21:55 +0000207{
Kumar Galaec1340d2007-11-27 23:25:02 -0600208 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
wdenk0aeb8532004-10-10 21:21:55 +0000209
wdenkef3386f2004-10-10 21:27:30 +0000210 /* PCI slot in USER bits CSR[6:7] by convention. */
211 uint pci_slot = get_pci_slot ();
wdenk0aeb8532004-10-10 21:21:55 +0000212
wdenkef3386f2004-10-10 21:27:30 +0000213 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
214 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
215 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
216 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
wdenk0aeb8532004-10-10 21:21:55 +0000217
wdenkef3386f2004-10-10 21:27:30 +0000218 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
wdenk0aeb8532004-10-10 21:21:55 +0000219
wdenkef3386f2004-10-10 21:27:30 +0000220 uint cpu_board_rev = get_cpu_board_revision ();
wdenk0aeb8532004-10-10 21:21:55 +0000221
wdenkef3386f2004-10-10 21:27:30 +0000222 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
223 get_board_version (), pci_slot);
wdenk0aeb8532004-10-10 21:21:55 +0000224
wdenkef3386f2004-10-10 21:27:30 +0000225 printf ("CPU Board Revision %d.%d (0x%04x)\n",
226 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
227 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
wdenk0aeb8532004-10-10 21:21:55 +0000228
wdenkef3386f2004-10-10 21:27:30 +0000229 printf (" PCI1: %d bit, %s MHz, %s\n",
230 (pci1_32) ? 32 : 64,
231 (pci1_speed == 33000000) ? "33" :
232 (pci1_speed == 66000000) ? "66" : "unknown",
233 pci1_clk_sel ? "sync" : "async");
wdenk0aeb8532004-10-10 21:21:55 +0000234
wdenkef3386f2004-10-10 21:27:30 +0000235 if (pci_dual) {
236 printf (" PCI2: 32 bit, 66 MHz, %s\n",
237 pci2_clk_sel ? "sync" : "async");
238 } else {
239 printf (" PCI2: disabled\n");
240 }
wdenk0aeb8532004-10-10 21:21:55 +0000241
wdenkef3386f2004-10-10 21:27:30 +0000242 /*
243 * Initialize local bus.
244 */
245 local_bus_init ();
wdenk0aeb8532004-10-10 21:21:55 +0000246
wdenkef3386f2004-10-10 21:27:30 +0000247 return 0;
wdenk0aeb8532004-10-10 21:21:55 +0000248}
249
wdenk0aeb8532004-10-10 21:21:55 +0000250long int
251initdram(int board_type)
252{
253 long dram_size = 0;
wdenk0aeb8532004-10-10 21:21:55 +0000254
255 puts("Initializing\n");
256
257#if defined(CONFIG_DDR_DLL)
258 {
259 /*
260 * Work around to stabilize DDR DLL MSYNC_IN.
261 * Errata DDR9 seems to have been fixed.
262 * This is now the workaround for Errata DDR11:
263 * Override DLL = 1, Course Adj = 1, Tap Select = 0
264 */
265
Kumar Galaec1340d2007-11-27 23:25:02 -0600266 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
wdenk0aeb8532004-10-10 21:21:55 +0000267
268 gur->ddrdllcr = 0x81000000;
269 asm("sync;isync;msync");
270 udelay(200);
271 }
272#endif
wdenk0aeb8532004-10-10 21:21:55 +0000273 dram_size = spd_sdram();
274
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500275#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk0aeb8532004-10-10 21:21:55 +0000276 /*
277 * Initialize and enable DDR ECC.
278 */
279 ddr_enable_ecc(dram_size);
280#endif
wdenk0aeb8532004-10-10 21:21:55 +0000281 /*
282 * SDRAM Initialization
283 */
284 sdram_init();
285
286 puts(" DDR: ");
287 return dram_size;
288}
289
wdenk0aeb8532004-10-10 21:21:55 +0000290/*
291 * Initialize Local Bus
292 */
wdenk0aeb8532004-10-10 21:21:55 +0000293void
294local_bus_init(void)
295{
Kumar Galaec1340d2007-11-27 23:25:02 -0600296 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Kumar Gala0a7a0972007-11-29 02:10:09 -0600297 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
wdenk0aeb8532004-10-10 21:21:55 +0000298
299 uint clkdiv;
300 uint lbc_hz;
301 sys_info_t sysinfo;
302 uint temp_lbcdll;
303
304 /*
305 * Errata LBC11.
306 * Fix Local Bus clock glitch when DLL is enabled.
307 *
308 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
309 * If localbus freq is > 133Mhz, DLL can be safely enabled.
310 * Between 66 and 133, the DLL is enabled with an override workaround.
311 */
312
313 get_sys_info(&sysinfo);
314 clkdiv = lbc->lcrr & 0x0f;
315 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
316
317 if (lbc_hz < 66) {
318 lbc->lcrr |= 0x80000000; /* DLL Bypass */
319
320 } else if (lbc_hz >= 133) {
321 lbc->lcrr &= (~0x80000000); /* DLL Enabled */
322
323 } else {
324 lbc->lcrr &= (~0x8000000); /* DLL Enabled */
325 udelay(200);
326
327 /*
328 * Sample LBC DLL ctrl reg, upshift it to set the
329 * override bits.
330 */
331 temp_lbcdll = gur->lbcdllcr;
332 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
333 asm("sync;isync;msync");
334 }
335}
336
wdenk0aeb8532004-10-10 21:21:55 +0000337/*
338 * Initialize SDRAM memory on the Local Bus.
339 */
wdenk0aeb8532004-10-10 21:21:55 +0000340void
341sdram_init(void)
342{
343#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
344
345 uint idx;
Kumar Gala0a7a0972007-11-29 02:10:09 -0600346 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
wdenk0aeb8532004-10-10 21:21:55 +0000347 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
348 uint cpu_board_rev;
349 uint lsdmr_common;
350
351 puts(" SDRAM: ");
352
353 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
354
355 /*
356 * Setup SDRAM Base and Option Registers
357 */
358 lbc->or2 = CFG_OR2_PRELIM;
359 asm("msync");
360
361 lbc->br2 = CFG_BR2_PRELIM;
362 asm("msync");
363
364 lbc->lbcr = CFG_LBC_LBCR;
365 asm("msync");
366
367
368 lbc->lsrt = CFG_LBC_LSRT;
369 lbc->mrtpr = CFG_LBC_MRTPR;
370 asm("msync");
371
372 /*
373 * Determine which address lines to use baed on CPU board rev.
374 */
375 cpu_board_rev = get_cpu_board_revision();
376 lsdmr_common = CFG_LBC_LSDMR_COMMON;
377 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
378 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
379 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
380 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
381 } else {
382 /*
383 * Assume something unable to identify itself is
384 * really old, and likely has lines 16/17 mapped.
385 */
386 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
387 }
388
389 /*
390 * Issue PRECHARGE ALL command.
391 */
392 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
393 asm("sync;msync");
394 *sdram_addr = 0xff;
395 ppcDcbf((unsigned long) sdram_addr);
396 udelay(100);
397
398 /*
399 * Issue 8 AUTO REFRESH commands.
400 */
401 for (idx = 0; idx < 8; idx++) {
402 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
403 asm("sync;msync");
404 *sdram_addr = 0xff;
405 ppcDcbf((unsigned long) sdram_addr);
406 udelay(100);
407 }
408
409 /*
410 * Issue 8 MODE-set command.
411 */
412 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
413 asm("sync;msync");
414 *sdram_addr = 0xff;
415 ppcDcbf((unsigned long) sdram_addr);
416 udelay(100);
417
418 /*
419 * Issue NORMAL OP command.
420 */
421 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
422 asm("sync;msync");
423 *sdram_addr = 0xff;
424 ppcDcbf((unsigned long) sdram_addr);
425 udelay(200); /* Overkill. Must wait > 200 bus cycles */
426
427#endif /* enable SDRAM init */
428}
429
wdenk0aeb8532004-10-10 21:21:55 +0000430#if defined(CFG_DRAM_TEST)
431int
432testdram(void)
433{
434 uint *pstart = (uint *) CFG_MEMTEST_START;
435 uint *pend = (uint *) CFG_MEMTEST_END;
436 uint *p;
437
438 printf("Testing DRAM from 0x%08x to 0x%08x\n",
439 CFG_MEMTEST_START,
440 CFG_MEMTEST_END);
441
442 printf("DRAM test phase 1:\n");
443 for (p = pstart; p < pend; p++)
444 *p = 0xaaaaaaaa;
445
446 for (p = pstart; p < pend; p++) {
447 if (*p != 0xaaaaaaaa) {
448 printf ("DRAM test fails at: %08x\n", (uint) p);
449 return 1;
450 }
451 }
452
453 printf("DRAM test phase 2:\n");
454 for (p = pstart; p < pend; p++)
455 *p = 0x55555555;
456
457 for (p = pstart; p < pend; p++) {
458 if (*p != 0x55555555) {
459 printf ("DRAM test fails at: %08x\n", (uint) p);
460 return 1;
461 }
462 }
463
464 printf("DRAM test passed.\n");
465 return 0;
466}
467#endif
468
wdenk0aeb8532004-10-10 21:21:55 +0000469#if defined(CONFIG_PCI)
Matthew McClintock3b662012006-06-28 10:46:13 -0500470/* For some reason the Tundra PCI bridge shows up on itself as a
471 * different device. Work around that by refusing to configure it.
wdenk0aeb8532004-10-10 21:21:55 +0000472 */
Matthew McClintock3b662012006-06-28 10:46:13 -0500473void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
wdenk0aeb8532004-10-10 21:21:55 +0000474
wdenk0aeb8532004-10-10 21:21:55 +0000475static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintock3b662012006-06-28 10:46:13 -0500476 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
Randy Vinson1dfd6d92007-02-27 19:42:22 -0700477 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
478 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
Andy Flemingdcd580b2007-02-24 01:08:13 -0600479 mpc85xx_config_via_usbide, {0,0,0}},
Randy Vinson1dfd6d92007-02-27 19:42:22 -0700480 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
481 mpc85xx_config_via_usb, {0,0,0}},
482 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
483 mpc85xx_config_via_usb2, {0,0,0}},
484 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
Andy Flemingdcd580b2007-02-24 01:08:13 -0600485 mpc85xx_config_via_power, {0,0,0}},
Randy Vinson1dfd6d92007-02-27 19:42:22 -0700486 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
487 mpc85xx_config_via_ac97, {0,0,0}},
Andy Flemingdcd580b2007-02-24 01:08:13 -0600488 {},
wdenk0aeb8532004-10-10 21:21:55 +0000489};
wdenk0aeb8532004-10-10 21:21:55 +0000490
Matthew McClintock3b662012006-06-28 10:46:13 -0500491static struct pci_controller hose[] = {
492 { config_table: pci_mpc85xxcds_config_table,},
493#ifdef CONFIG_MPC85XX_PCI2
494 {},
wdenk0aeb8532004-10-10 21:21:55 +0000495#endif
496};
497
498#endif /* CONFIG_PCI */
499
wdenk0aeb8532004-10-10 21:21:55 +0000500void
501pci_init_board(void)
502{
503#ifdef CONFIG_PCI
Matthew McClintock5b948822006-10-11 15:13:01 -0500504 pci_mpc85xx_init(hose);
wdenk0aeb8532004-10-10 21:21:55 +0000505#endif
506}
Kumar Galad28ced32007-11-29 00:11:44 -0600507
508#if defined(CONFIG_OF_BOARD_SETUP)
509void
510ft_pci_setup(void *blob, bd_t *bd)
511{
512 int node, tmp[2];
513 const char *path;
514
515 node = fdt_path_offset(blob, "/aliases");
516 tmp[0] = 0;
517 if (node >= 0) {
518#ifdef CONFIG_PCI1
519 path = fdt_getprop(blob, node, "pci0", NULL);
520 if (path) {
521 tmp[1] = hose[0].last_busno - hose[0].first_busno;
522 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
523 }
524#endif
525#ifdef CONFIG_MPC85XX_PCI2
526 path = fdt_getprop(blob, node, "pci1", NULL);
527 if (path) {
528 tmp[1] = hose[1].last_busno - hose[1].first_busno;
529 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
530 }
531#endif
532 }
533}
534#endif