Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / d4bf08b6092998eaaeea96185b0c95b9364cb486 / . / configs / firefly-rk3399_defconfig
blob: 5475172532888e058d2fa3a0c0602a59ff91e71d [file] [log] [blame]
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]5CONFIG_TEXT_BASE=0x00200000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=1
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]7CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]9CONFIG_ROCKCHIP_RK3399=y
Kever Yang1b662092020-02-19 17:51:07 +0800[diff] [blame]10CONFIG_TARGET_EVB_RK3399=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]11CONFIG_DEBUG_UART_BASE=0xFF1A0000
12CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]13CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]14CONFIG_DEBUG_UART=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]15CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
16CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]17CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]18CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]19CONFIG_MISC_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]20CONFIG_SPL_MAX_SIZE=0x2e000
21CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame]22CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
23CONFIG_SPL_BSS_START_ADDR=0x400000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]24CONFIG_SPL_BSS_MAX_SIZE=0x2000
Kever Yang20673542019-08-20 11:47:02 +0800[diff] [blame]25# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]26# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
27CONFIG_SPL_STACK=0x400000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]28CONFIG_SPL_STACK_R=y
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]29CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]30CONFIG_TPL=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]31CONFIG_CMD_BOOTZ=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]32CONFIG_CMD_GPT=y
33CONFIG_CMD_MMC=y
Mark Kettenisb01f4c42020-05-25 11:00:56 +0200[diff] [blame]34CONFIG_CMD_PCI=y
Tom Rini52f34042020-06-23 08:20:07 -0400[diff] [blame]35CONFIG_CMD_USB=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]36# CONFIG_CMD_SETEXPR is not set
37CONFIG_CMD_TIME=y
38CONFIG_SPL_OF_CONTROL=y
39CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]40CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]41CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]42CONFIG_ROCKCHIP_GPIO=y
43CONFIG_SYS_I2C_ROCKCHIP=y
Mark Kettenisc85f5392020-01-13 11:39:16 +0100[diff] [blame]44CONFIG_MISC=y
45CONFIG_ROCKCHIP_EFUSE=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]46CONFIG_MMC_DW=y
Kever Yangd4335fc2017-06-14 16:31:48 +0800[diff] [blame]47CONFIG_MMC_DW_ROCKCHIP=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]48CONFIG_MMC_SDHCI=y
49CONFIG_MMC_SDHCI_ROCKCHIP=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]50CONFIG_SF_DEFAULT_SPEED=20000000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]51CONFIG_ETH_DESIGNWARE=y
52CONFIG_GMAC_ROCKCHIP=y
Mark Kettenisf8463d62022-01-22 20:38:11 +0100[diff] [blame]53CONFIG_NVME_PCI=y
Mark Kettenisb01f4c42020-05-25 11:00:56 +0200[diff] [blame]54CONFIG_PCI=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]55CONFIG_PMIC_RK8XX=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]56CONFIG_REGULATOR_PWM=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]57CONFIG_REGULATOR_RK8XX=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]58CONFIG_PWM_ROCKCHIP=y
Mark Kettenisb01f4c42020-05-25 11:00:56 +0200[diff] [blame]59CONFIG_DM_RESET=y
Tom Rinib2e0b322021-01-29 13:56:04 -0500[diff] [blame]60CONFIG_DM_RNG=y
61CONFIG_RNG_ROCKCHIP=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]62CONFIG_BAUDRATE=1500000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]63CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]64CONFIG_SYS_NS16550_MEM32=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]65CONFIG_SYSRESET=y
66CONFIG_USB=y
67CONFIG_USB_XHCI_HCD=y
68CONFIG_USB_XHCI_DWC3=y
69CONFIG_USB_EHCI_HCD=y
70CONFIG_USB_EHCI_GENERIC=y
Kever Yangcd1810c2020-07-22 19:46:19 +0800[diff] [blame]71CONFIG_USB_DWC3=y
72CONFIG_USB_DWC3_GENERIC=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]73CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]74CONFIG_USB_ETHER_ASIX=y
75CONFIG_USB_ETHER_ASIX88179=y
76CONFIG_USB_ETHER_MCS7830=y
77CONFIG_USB_ETHER_RTL8152=y
78CONFIG_USB_ETHER_SMSC95XX=y
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]79CONFIG_SPL_TINY_MEMSET=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]80CONFIG_ERRNO_STR=y