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git01.mediatek.com / filogic / uboot / 5cd7ece36927cab1fb501c62f14400fb11371736 / . / configs / firefly-rk3399_defconfig
blob: b84d7b9ff0a5c129effca8363d03e32dbe209ff3 [file] [log] [blame]
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x00200000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]4CONFIG_ROCKCHIP_RK3399=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame^]5CONFIG_ENV_OFFSET=0x3F8000
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=1
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]7CONFIG_DEBUG_UART_BASE=0xFF1A0000
8CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]9CONFIG_DEBUG_UART=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]10CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]11# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]12CONFIG_DISPLAY_BOARDINFO_LATE=y
Kever Yang20673542019-08-20 11:47:02 +0800[diff] [blame]13# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]14CONFIG_SPL_STACK_R=y
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]15CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]16CONFIG_TPL=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]17CONFIG_CMD_BOOTZ=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]18CONFIG_CMD_GPT=y
19CONFIG_CMD_MMC=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]20CONFIG_CMD_USB=y
21# CONFIG_CMD_SETEXPR is not set
22CONFIG_CMD_TIME=y
23CONFIG_SPL_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]24CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]25CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]26CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]27CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]28CONFIG_ROCKCHIP_GPIO=y
29CONFIG_SYS_I2C_ROCKCHIP=y
30CONFIG_MMC_DW=y
Kever Yangd4335fc2017-06-14 16:31:48 +0800[diff] [blame]31CONFIG_MMC_DW_ROCKCHIP=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]32CONFIG_MMC_SDHCI=y
33CONFIG_MMC_SDHCI_ROCKCHIP=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]34CONFIG_SF_DEFAULT_SPEED=20000000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]35CONFIG_DM_ETH=y
36CONFIG_ETH_DESIGNWARE=y
37CONFIG_GMAC_ROCKCHIP=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]38CONFIG_PMIC_RK8XX=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]39CONFIG_REGULATOR_PWM=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]40CONFIG_REGULATOR_RK8XX=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]41CONFIG_PWM_ROCKCHIP=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]42CONFIG_BAUDRATE=1500000
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]43CONFIG_DEBUG_UART_SHIFT=2
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]44CONFIG_SYSRESET=y
45CONFIG_USB=y
46CONFIG_USB_XHCI_HCD=y
47CONFIG_USB_XHCI_DWC3=y
48CONFIG_USB_EHCI_HCD=y
49CONFIG_USB_EHCI_GENERIC=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]50CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]51CONFIG_USB_ETHER_ASIX=y
52CONFIG_USB_ETHER_ASIX88179=y
53CONFIG_USB_ETHER_MCS7830=y
54CONFIG_USB_ETHER_RTL8152=y
55CONFIG_USB_ETHER_SMSC95XX=y
Kever Yangb5aba0d2018-11-09 11:21:38 +0800[diff] [blame]56CONFIG_SPL_TINY_MEMSET=y
Kever Yang6d43fb12017-04-24 11:58:30 +0800[diff] [blame]57CONFIG_ERRNO_STR=y