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git01.mediatek.com / filogic / uboot / d4b57ec1d154916492fefd33ded0b3c2a7daff00 / . / arch / arm / mach-tegra / tegra210 / clock.c
blob: 57ff0b2a19afec2e2fc41086c78779c39b8c2481 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]2/*
Tom Warren3bb2f5d2020-03-27 10:24:31 -0700[diff] [blame]3 * (C) Copyright 2013-2020
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]4 * NVIDIA Corporation <www.nvidia.com>
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]5 */
6
7/* Tegra210 Clock control functions */
8
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]9#include <errno.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]10#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]11#include <log.h>
Tom Rini2f8362d2024-04-30 07:35:31 -0600[diff] [blame]12#include <time.h>
Simon Glass274e0b02020-05-10 11:39:56 -0600[diff] [blame]13#include <asm/cache.h>
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]14#include <asm/io.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/sysctr.h>
17#include <asm/arch/tegra.h>
18#include <asm/arch-tegra/clk_rst.h>
19#include <asm/arch-tegra/timer.h>
20#include <div64.h>
21#include <fdtdec.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]22#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -0600[diff] [blame]23#include <linux/delay.h>
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]24
Svyatoslav Ryhel19a5b032023-02-14 19:35:25 +0200[diff] [blame]25#include <dt-bindings/clock/tegra210-car.h>
26
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]27/*
28 * Clock types that we can use as a source. The Tegra210 has muxes for the
29 * peripheral clocks, and in most cases there are four options for the clock
30 * source. This gives us a clock 'type' and exploits what commonality exists
31 * in the device.
32 *
33 * Letters are obvious, except for T which means CLK_M, and S which means the
34 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
35 * datasheet) and PLL_M are different things. The former is the basic
36 * clock supplied to the SOC from an external oscillator. The latter is the
37 * memory clock PLL.
38 *
39 * See definitions in clock_id in the header file.
40 */
41enum clock_type_id {
42 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
43 CLOCK_TYPE_MCPA, /* and so on */
44 CLOCK_TYPE_MCPT,
45 CLOCK_TYPE_PCM,
46 CLOCK_TYPE_PCMT,
47 CLOCK_TYPE_PDCT,
48 CLOCK_TYPE_ACPT,
49 CLOCK_TYPE_ASPTE,
Thierry Reding317a47c2019-04-15 11:32:15 +0200[diff] [blame]50 CLOCK_TYPE_PDD2T,
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]51 CLOCK_TYPE_PCST,
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600[diff] [blame]52 CLOCK_TYPE_DP,
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]53
54 CLOCK_TYPE_PC2CC3M,
55 CLOCK_TYPE_PC2CC3S_T,
56 CLOCK_TYPE_PC2CC3M_T,
57 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
58 CLOCK_TYPE_MC2CC3P_A,
59 CLOCK_TYPE_M,
60 CLOCK_TYPE_MCPTM2C2C3,
61 CLOCK_TYPE_PC2CC3T_S,
62 CLOCK_TYPE_AC2CC3P_TS2,
63 CLOCK_TYPE_PC01C00_C42C41TC40,
64
65 CLOCK_TYPE_COUNT,
66 CLOCK_TYPE_NONE = -1, /* invalid clock type */
67};
68
69enum {
70 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
71};
72
73/*
74 * Clock source mux for each clock type. This just converts our enum into
75 * a list of mux sources for use by the code.
76 *
77 * Note:
78 * The extra column in each clock source array is used to store the mask
79 * bits in its register for the source.
80 */
81#define CLK(x) CLOCK_ID_ ## x
82static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
83 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
85 MASK_BITS_31_30},
86 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
88 MASK_BITS_31_30},
89 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
90 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
91 MASK_BITS_31_30},
92 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
93 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
94 MASK_BITS_31_30},
95 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
97 MASK_BITS_31_30},
98 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
99 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
100 MASK_BITS_31_30},
101 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
102 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
103 MASK_BITS_31_30},
104 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
105 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
106 MASK_BITS_31_29},
Thierry Reding317a47c2019-04-15 11:32:15 +0200[diff] [blame]107 { CLK(PERIPH), CLK(NONE), CLK(DISPLAY), CLK(NONE),
108 CLK(NONE), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]109 MASK_BITS_31_29},
110 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
111 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
112 MASK_BITS_31_28},
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600[diff] [blame]113 /* CLOCK_TYPE_DP */
114 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
115 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
116 MASK_BITS_31_28},
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]117
118 /* Additional clock types on Tegra114+ */
119 /* CLOCK_TYPE_PC2CC3M */
120 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
121 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
122 MASK_BITS_31_29},
123 /* CLOCK_TYPE_PC2CC3S_T */
124 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
125 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
126 MASK_BITS_31_29},
127 /* CLOCK_TYPE_PC2CC3M_T */
128 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
129 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
130 MASK_BITS_31_29},
131 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
132 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
133 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
134 MASK_BITS_31_29},
135 /* CLOCK_TYPE_MC2CC3P_A */
136 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
137 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
138 MASK_BITS_31_29},
139 /* CLOCK_TYPE_M */
140 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
141 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
142 MASK_BITS_31_30},
143 /* CLOCK_TYPE_MCPTM2C2C3 */
144 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
145 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
146 MASK_BITS_31_29},
147 /* CLOCK_TYPE_PC2CC3T_S */
148 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
149 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
150 MASK_BITS_31_29},
151 /* CLOCK_TYPE_AC2CC3P_TS2 */
152 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
153 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
154 MASK_BITS_31_29},
155 /* CLOCK_TYPE_PC01C00_C42C41TC40 */
156 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
157 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
158 MASK_BITS_31_29},
159};
160
161/*
162 * Clock type for each peripheral clock source. We put the name in each
163 * record just so it is easy to match things up
164 */
165#define TYPE(name, type) type
166static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
167 /* 0x00 */
168 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
169 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
170 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
171 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
172 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
173 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
174 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
175 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
176
177 /* 0x08 */
178 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
179 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
180 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
181 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
182 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
183 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
Thierry Reding317a47c2019-04-15 11:32:15 +0200[diff] [blame]184 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDD2T),
185 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDD2T),
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]186
187 /* 0x10 */
188 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
189 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
190 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
191 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
192 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
193 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
194 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
195 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
196
197 /* 0x18 */
198 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
199 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
200 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
201 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
202 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
203 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
204 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
205 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
206
207 /* 0x20 */
208 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
209 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
211 TYPE(PERIPHC_23h, CLOCK_TYPE_NONE),
212 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
213 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
214 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
215 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
216
217 /* 0x28 */
218 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
219 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
220 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
221 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
222 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
223 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
224 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
225 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
226
227 /* 0x30 */
228 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
229 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
230 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
231 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
232 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
233 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
234 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
235 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
236
237 /* 0x38 */
238 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
239 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
240 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
241 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
242 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
243 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
244 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
245 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
246
247 /* 0x40 */
248 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
249 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
250 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
251 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
252 TYPE(PERIPHC_I2S5, CLOCK_TYPE_AXPT),
253 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
254 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
255 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
256
257 /* 0x48 */
258 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
259 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
260 TYPE(PERIPHC_4ah, CLOCK_TYPE_NONE),
261 TYPE(PERIPHC_4bh, CLOCK_TYPE_NONE),
262 TYPE(PERIPHC_4ch, CLOCK_TYPE_NONE),
263 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
264 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
265 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
266
267 /* 0x50 */
268 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
269 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
270 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
271 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
272 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
273 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
274 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
275 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
276
277 /* 0x58 */
278 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
279 TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
280 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
281 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
282 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
283 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
284 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
285 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
286
287 /* 0x60 */
288 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
289 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
290 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
291 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
292 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
293 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
294 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
295 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
296
297 /* 0x68 */
298 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
299 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
300 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
301 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
302 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
303 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
304 TYPE(PERIPHC_6eh, CLOCK_TYPE_NONE),
305 TYPE(PERIPHC_6fh, CLOCK_TYPE_NONE),
306
307 /* 0x70 */
308 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
309 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
310 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
311 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
312 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
313 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
314 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
315 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
316
317 /* 0x78 */
318 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
319 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
320 TYPE(PERIPHC_7ah, CLOCK_TYPE_NONE),
321 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
322 TYPE(PERIPHC_7ch, CLOCK_TYPE_NONE),
323 TYPE(PERIPHC_7dh, CLOCK_TYPE_NONE),
324 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
325 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
326
327 /* 0x80 */
328 TYPE(PERIPHC_SDMMC_LEGACY_TM, CLOCK_TYPE_NONE),
329 TYPE(PERIPHC_NVDEC, CLOCK_TYPE_NONE),
330 TYPE(PERIPHC_NVJPG, CLOCK_TYPE_NONE),
331 TYPE(PERIPHC_NVENC, CLOCK_TYPE_NONE),
332 TYPE(PERIPHC_84h, CLOCK_TYPE_NONE),
333 TYPE(PERIPHC_85h, CLOCK_TYPE_NONE),
334 TYPE(PERIPHC_86h, CLOCK_TYPE_NONE),
335 TYPE(PERIPHC_87h, CLOCK_TYPE_NONE),
336
337 /* 0x88 */
338 TYPE(PERIPHC_88h, CLOCK_TYPE_NONE),
339 TYPE(PERIPHC_89h, CLOCK_TYPE_NONE),
340 TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
341 TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
342 TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
Tom Warren3bb2f5d2020-03-27 10:24:31 -0700[diff] [blame]343 TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16),
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]344 TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
345 TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
346
347 /* 0x90 */
348 TYPE(PERIPHC_MAUD, CLOCK_TYPE_NONE),
349 TYPE(PERIPHC_TSECB, CLOCK_TYPE_NONE),
350};
351
352/*
353 * This array translates a periph_id to a periphc_internal_id
354 *
355 * Not present/matched up:
356 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
357 * SPDIF - which is both 0x08 and 0x0c
358 *
359 */
360#define NONE(name) (-1)
361#define OFFSET(name, value) PERIPHC_ ## name
362#define INTERNAL_ID(id) (id & 0x000000ff)
363static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
364 /* Low word: 31:0 */
365 NONE(CPU),
366 NONE(COP),
367 NONE(TRIGSYS),
368 NONE(ISPB),
369 NONE(RESERVED4),
370 NONE(TMR),
371 PERIPHC_UART1,
372 PERIPHC_UART2, /* and vfir 0x68 */
373
374 /* 8 */
375 NONE(GPIO),
376 PERIPHC_SDMMC2,
377 PERIPHC_SPDIF_IN,
378 PERIPHC_I2S2,
379 PERIPHC_I2C1,
380 NONE(RESERVED13),
381 PERIPHC_SDMMC1,
382 PERIPHC_SDMMC4,
383
384 /* 16 */
385 NONE(TCW),
386 PERIPHC_PWM,
387 PERIPHC_I2S3,
388 NONE(RESERVED19),
389 PERIPHC_VI,
390 NONE(RESERVED21),
391 NONE(USBD),
392 NONE(ISP),
393
394 /* 24 */
395 NONE(RESERVED24),
396 NONE(RESERVED25),
397 PERIPHC_DISP2,
398 PERIPHC_DISP1,
399 PERIPHC_HOST1X,
400 NONE(VCP),
401 PERIPHC_I2S1,
402 NONE(CACHE2),
403
404 /* Middle word: 63:32 */
405 NONE(MEM),
406 NONE(AHBDMA),
407 NONE(APBDMA),
408 NONE(RESERVED35),
409 NONE(RESERVED36),
410 NONE(STAT_MON),
411 NONE(RESERVED38),
412 NONE(FUSE),
413
414 /* 40 */
415 NONE(KFUSE),
416 PERIPHC_SBC1, /* SBCx = SPIx */
417 PERIPHC_NOR,
418 NONE(RESERVED43),
419 PERIPHC_SBC2,
420 NONE(XIO),
421 PERIPHC_SBC3,
422 PERIPHC_I2C5,
423
424 /* 48 */
425 NONE(DSI),
426 NONE(RESERVED49),
427 PERIPHC_HSI,
428 NONE(RESERVED51),
429 NONE(CSI),
430 NONE(RESERVED53),
431 PERIPHC_I2C2,
432 PERIPHC_UART3,
433
434 /* 56 */
435 NONE(MIPI_CAL),
436 PERIPHC_EMC,
437 NONE(USB2),
438 NONE(USB3),
439 NONE(RESERVED60),
440 PERIPHC_VDE,
441 NONE(BSEA),
442 NONE(BSEV),
443
444 /* Upper word 95:64 */
445 NONE(RESERVED64),
446 PERIPHC_UART4,
447 PERIPHC_UART5,
448 PERIPHC_I2C3,
449 PERIPHC_SBC4,
450 PERIPHC_SDMMC3,
451 NONE(PCIE),
452 PERIPHC_OWR,
453
454 /* 72 */
455 NONE(AFI),
456 PERIPHC_CSITE,
457 NONE(PCIEXCLK),
458 NONE(AVPUCQ),
459 NONE(LA),
460 NONE(TRACECLKIN),
461 NONE(SOC_THERM),
462 NONE(DTV),
463
464 /* 80 */
465 NONE(RESERVED80),
466 PERIPHC_I2CSLOW,
467 NONE(DSIB),
468 PERIPHC_TSEC,
469 NONE(RESERVED84),
470 NONE(RESERVED85),
471 NONE(RESERVED86),
472 NONE(EMUCIF),
473
474 /* 88 */
475 NONE(RESERVED88),
476 NONE(XUSB_HOST),
477 NONE(RESERVED90),
478 PERIPHC_MSENC,
479 NONE(RESERVED92),
480 NONE(RESERVED93),
481 NONE(RESERVED94),
482 NONE(XUSB_DEV),
483
484 /* V word: 31:0 */
485 NONE(CPUG),
486 NONE(CPULP),
487 NONE(V_RESERVED2),
488 PERIPHC_MSELECT,
489 NONE(V_RESERVED4),
490 PERIPHC_I2S4,
491 PERIPHC_I2S5,
492 PERIPHC_I2C4,
493
494 /* 104 */
495 PERIPHC_SBC5,
496 PERIPHC_SBC6,
497 PERIPHC_AUDIO,
498 NONE(APBIF),
499 NONE(V_RESERVED12),
500 NONE(V_RESERVED13),
501 NONE(V_RESERVED14),
502 PERIPHC_HDA2CODEC2X,
503
504 /* 112 */
505 NONE(ATOMICS),
506 NONE(V_RESERVED17),
507 NONE(V_RESERVED18),
508 NONE(V_RESERVED19),
509 NONE(V_RESERVED20),
510 NONE(V_RESERVED21),
511 NONE(V_RESERVED22),
512 PERIPHC_ACTMON,
513
514 /* 120 */
515 NONE(EXTPERIPH1),
516 NONE(EXTPERIPH2),
517 NONE(EXTPERIPH3),
518 NONE(OOB),
519 PERIPHC_SATA,
520 PERIPHC_HDA,
521 NONE(TZRAM),
522 NONE(SE),
523
524 /* W word: 31:0 */
525 NONE(HDA2HDMICODEC),
526 NONE(SATACOLD),
527 NONE(W_RESERVED2),
528 NONE(W_RESERVED3),
529 NONE(W_RESERVED4),
530 NONE(W_RESERVED5),
531 NONE(W_RESERVED6),
532 NONE(W_RESERVED7),
533
534 /* 136 */
535 NONE(CEC),
536 NONE(W_RESERVED9),
537 NONE(W_RESERVED10),
538 NONE(W_RESERVED11),
539 NONE(W_RESERVED12),
540 NONE(W_RESERVED13),
541 NONE(XUSB_PADCTL),
542 NONE(W_RESERVED15),
543
544 /* 144 */
545 NONE(W_RESERVED16),
546 NONE(W_RESERVED17),
547 NONE(W_RESERVED18),
548 NONE(W_RESERVED19),
549 NONE(W_RESERVED20),
550 NONE(ENTROPY),
551 NONE(DDS),
552 NONE(W_RESERVED23),
553
554 /* 152 */
555 NONE(W_RESERVED24),
556 NONE(W_RESERVED25),
557 NONE(W_RESERVED26),
558 NONE(DVFS),
559 NONE(XUSB_SS),
560 NONE(W_RESERVED29),
561 NONE(W_RESERVED30),
562 NONE(W_RESERVED31),
563
564 /* X word: 31:0 */
565 NONE(SPARE),
566 NONE(X_RESERVED1),
567 NONE(X_RESERVED2),
568 NONE(X_RESERVED3),
569 NONE(CAM_MCLK),
570 NONE(CAM_MCLK2),
571 PERIPHC_I2C6,
572 NONE(X_RESERVED7),
573
574 /* 168 */
575 NONE(X_RESERVED8),
576 NONE(X_RESERVED9),
577 NONE(X_RESERVED10),
578 NONE(VIM2_CLK),
579 NONE(X_RESERVED12),
580 NONE(X_RESERVED13),
581 NONE(EMC_DLL),
582 NONE(X_RESERVED15),
583
584 /* 176 */
585 NONE(X_RESERVED16),
586 NONE(CLK72MHZ),
587 NONE(VIC),
588 NONE(X_RESERVED19),
589 NONE(X_RESERVED20),
590 NONE(DPAUX),
591 NONE(SOR0),
592 NONE(X_RESERVED23),
593
594 /* 184 */
595 NONE(GPU),
596 NONE(X_RESERVED25),
597 NONE(X_RESERVED26),
598 NONE(X_RESERVED27),
599 NONE(X_RESERVED28),
600 NONE(X_RESERVED29),
601 NONE(X_RESERVED30),
602 NONE(X_RESERVED31),
603
604 /* Y: 192 (192 - 223) */
605 NONE(Y_RESERVED0),
606 PERIPHC_SDMMC_LEGACY_TM,
607 PERIPHC_NVDEC,
608 PERIPHC_NVJPG,
609 NONE(Y_RESERVED4),
610 PERIPHC_DMIC3, /* 197 */
611 PERIPHC_APE, /* 198 */
612 NONE(Y_RESERVED7),
613
614 /* 200 */
615 NONE(Y_RESERVED8),
616 NONE(Y_RESERVED9),
617 NONE(Y_RESERVED10),
618 NONE(Y_RESERVED11),
619 NONE(Y_RESERVED12),
620 NONE(Y_RESERVED13),
621 NONE(Y_RESERVED14),
622 NONE(Y_RESERVED15),
623
624 /* 208 */
625 PERIPHC_VI_I2C, /* 208 */
626 NONE(Y_RESERVED17),
627 NONE(Y_RESERVED18),
628 PERIPHC_QSPI, /* 211 */
629 NONE(Y_RESERVED20),
630 NONE(Y_RESERVED21),
631 NONE(Y_RESERVED22),
632 NONE(Y_RESERVED23),
633
634 /* 216 */
635 NONE(Y_RESERVED24),
636 NONE(Y_RESERVED25),
637 NONE(Y_RESERVED26),
638 PERIPHC_NVENC, /* 219 */
639 NONE(Y_RESERVED28),
640 NONE(Y_RESERVED29),
641 NONE(Y_RESERVED30),
642 NONE(Y_RESERVED31),
643};
644
645/*
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]646 * PLL divider shift/mask tables for all PLL IDs.
647 */
648struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
649 /*
650 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLC, etc.)
651 * If lock_ena or lock_det are >31, they're not used in that PLL (PLLC, etc.)
652 */
653 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
654 .lock_ena = 32, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLC */
655 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
656 .lock_ena = 4, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
657 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
658 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 3, .kvco_shift = 2, .kvco_mask = 1 }, /* PLLP */
659 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
660 .lock_ena = 28, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLA */
661 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F,
662 .lock_ena = 29, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLU */
663 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07,
664 .lock_ena = 18, .lock_det = 27, .kcp_shift = 23, .kcp_mask = 3, .kvco_shift = 22, .kvco_mask = 1 }, /* PLLD */
665 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
666 .lock_ena = 18, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLX */
667 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
668 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
669 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
670 .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/
Simon Glassb6ba3fb2015-08-10 07:14:36 -0600[diff] [blame]671 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
672 .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]673};
674
675/*
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]676 * Get the oscillator frequency, from the corresponding hardware configuration
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200[diff] [blame]677 * field. Note that T30+ supports 3 new higher freqs.
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]678 */
679enum clock_osc_freq clock_get_osc_freq(void)
680{
681 struct clk_rst_ctlr *clkrst =
682 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
683 u32 reg;
684
685 reg = readl(&clkrst->crc_osc_ctrl);
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200[diff] [blame]686 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]687}
688
689/* Returns a pointer to the clock source register for a peripheral */
690u32 *get_periph_source_reg(enum periph_id periph_id)
691{
692 struct clk_rst_ctlr *clkrst =
693 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
694 enum periphc_internal_id internal_id;
695
696 /* Coresight is a special case */
697 if (periph_id == PERIPH_ID_CSI)
698 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
699
700 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
701 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
702 assert(internal_id != -1);
703
704 if (internal_id < PERIPHC_VW_FIRST)
705 /* L, H, U */
706 return &clkrst->crc_clk_src[internal_id];
707
708 if (internal_id < PERIPHC_X_FIRST) {
709 /* VW */
710 internal_id -= PERIPHC_VW_FIRST;
711 return &clkrst->crc_clk_src_vw[internal_id];
712 }
713
714 if (internal_id < PERIPHC_Y_FIRST) {
715 /* X */
716 internal_id -= PERIPHC_X_FIRST;
717 return &clkrst->crc_clk_src_x[internal_id];
718 }
719
720 /* Y */
721 internal_id -= PERIPHC_Y_FIRST;
722 return &clkrst->crc_clk_src_y[internal_id];
723}
724
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]725int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
726 int *divider_bits, int *type)
727{
728 enum periphc_internal_id internal_id;
729
730 if (!clock_periph_id_isvalid(periph_id))
731 return -1;
732
Tom Warren3bb2f5d2020-03-27 10:24:31 -0700[diff] [blame]733 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]734 if (!periphc_internal_id_isvalid(internal_id))
735 return -1;
736
737 *type = clock_periph_type[internal_id];
738 if (!clock_type_id_isvalid(*type))
739 return -1;
740
741 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
742
743 if (*type == CLOCK_TYPE_PC2CC3M_T16)
744 *divider_bits = 16;
745 else
746 *divider_bits = 8;
747
748 return 0;
749}
750
751enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
752{
753 enum periphc_internal_id internal_id;
754 int type;
755
756 if (!clock_periph_id_isvalid(periph_id))
757 return CLOCK_ID_NONE;
758
Tom Warren3bb2f5d2020-03-27 10:24:31 -0700[diff] [blame]759 internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]760 if (!periphc_internal_id_isvalid(internal_id))
761 return CLOCK_ID_NONE;
762
763 type = clock_periph_type[internal_id];
764 if (!clock_type_id_isvalid(type))
765 return CLOCK_ID_NONE;
766
767 return clock_source[type][source];
768}
769
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]770/**
771 * Given a peripheral ID and the required source clock, this returns which
772 * value should be programmed into the source mux for that peripheral.
773 *
774 * There is special code here to handle the one source type with 5 sources.
775 *
776 * @param periph_id peripheral to start
777 * @param source PLL id of required parent clock
778 * @param mux_bits Set to number of bits in mux register: 2 or 4
779 * @param divider_bits Set to number of divider bits (8 or 16)
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100[diff] [blame]780 * Return: mux value (0-4, or -1 if not found)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]781 */
782int get_periph_clock_source(enum periph_id periph_id,
783 enum clock_id parent, int *mux_bits, int *divider_bits)
784{
785 enum clock_type_id type;
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]786 int mux, err;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]787
Stephen Warren532543c2016-09-13 10:45:56 -0600[diff] [blame]788 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
789 assert(!err);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]790
791 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
792 if (clock_source[type][mux] == parent)
793 return mux;
794
795 /* if we get here, either us or the caller has made a mistake */
796 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
797 parent);
798 return -1;
799}
800
801void clock_set_enable(enum periph_id periph_id, int enable)
802{
803 struct clk_rst_ctlr *clkrst =
804 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
805 u32 *clk;
806 u32 reg;
807
808 /* Enable/disable the clock to this peripheral */
809 assert(clock_periph_id_isvalid(periph_id));
810 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
811 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
812 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
813 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
814 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
815 clk = &clkrst->crc_clk_out_enb_x;
816 else
817 clk = &clkrst->crc_clk_out_enb_y;
818
819 reg = readl(clk);
820 if (enable)
821 reg |= PERIPH_MASK(periph_id);
822 else
823 reg &= ~PERIPH_MASK(periph_id);
824 writel(reg, clk);
825}
826
827void reset_set_enable(enum periph_id periph_id, int enable)
828{
829 struct clk_rst_ctlr *clkrst =
830 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
831 u32 *reset;
832 u32 reg;
833
834 /* Enable/disable reset to the peripheral */
835 assert(clock_periph_id_isvalid(periph_id));
836 if (periph_id < PERIPH_ID_VW_FIRST)
837 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
838 else if ((int)periph_id < (int)PERIPH_ID_X_FIRST)
839 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
840 else if ((int)periph_id < (int)PERIPH_ID_Y_FIRST)
841 reset = &clkrst->crc_rst_devices_x;
842 else
843 reset = &clkrst->crc_rst_devices_y;
844
845 reg = readl(reset);
846 if (enable)
847 reg |= PERIPH_MASK(periph_id);
848 else
849 reg &= ~PERIPH_MASK(periph_id);
850 writel(reg, reset);
851}
852
853#ifdef CONFIG_OF_CONTROL
854/*
855 * Convert a device tree clock ID to our peripheral ID. They are mostly
856 * the same but we are very cautious so we check that a valid clock ID is
857 * provided.
858 *
859 * @param clk_id Clock ID according to tegra210 device tree binding
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100[diff] [blame]860 * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]861 */
862enum periph_id clk_id_to_periph_id(int clk_id)
863{
864 if (clk_id > PERIPH_ID_COUNT)
865 return PERIPH_ID_NONE;
866
867 switch (clk_id) {
868 case PERIPH_ID_RESERVED4:
869 case PERIPH_ID_RESERVED25:
870 case PERIPH_ID_RESERVED35:
871 case PERIPH_ID_RESERVED36:
872 case PERIPH_ID_RESERVED38:
873 case PERIPH_ID_RESERVED43:
874 case PERIPH_ID_RESERVED49:
875 case PERIPH_ID_RESERVED53:
876 case PERIPH_ID_RESERVED64:
877 case PERIPH_ID_RESERVED84:
878 case PERIPH_ID_RESERVED85:
879 case PERIPH_ID_RESERVED86:
880 case PERIPH_ID_RESERVED88:
881 case PERIPH_ID_RESERVED90:
882 case PERIPH_ID_RESERVED92:
883 case PERIPH_ID_RESERVED93:
884 case PERIPH_ID_RESERVED94:
885 case PERIPH_ID_V_RESERVED2:
886 case PERIPH_ID_V_RESERVED4:
887 case PERIPH_ID_V_RESERVED17:
888 case PERIPH_ID_V_RESERVED18:
889 case PERIPH_ID_V_RESERVED19:
890 case PERIPH_ID_V_RESERVED20:
891 case PERIPH_ID_V_RESERVED21:
892 case PERIPH_ID_V_RESERVED22:
893 case PERIPH_ID_W_RESERVED2:
894 case PERIPH_ID_W_RESERVED3:
895 case PERIPH_ID_W_RESERVED4:
896 case PERIPH_ID_W_RESERVED5:
897 case PERIPH_ID_W_RESERVED6:
898 case PERIPH_ID_W_RESERVED7:
899 case PERIPH_ID_W_RESERVED9:
900 case PERIPH_ID_W_RESERVED10:
901 case PERIPH_ID_W_RESERVED11:
902 case PERIPH_ID_W_RESERVED12:
903 case PERIPH_ID_W_RESERVED13:
904 case PERIPH_ID_W_RESERVED15:
905 case PERIPH_ID_W_RESERVED16:
906 case PERIPH_ID_W_RESERVED17:
907 case PERIPH_ID_W_RESERVED18:
908 case PERIPH_ID_W_RESERVED19:
909 case PERIPH_ID_W_RESERVED20:
910 case PERIPH_ID_W_RESERVED23:
911 case PERIPH_ID_W_RESERVED29:
912 case PERIPH_ID_W_RESERVED30:
913 case PERIPH_ID_W_RESERVED31:
914 return PERIPH_ID_NONE;
915 default:
916 return clk_id;
917 }
918}
Svyatoslav Ryhel19a5b032023-02-14 19:35:25 +0200[diff] [blame]919
920/*
921 * Convert a device tree clock ID to our PLL ID.
922 *
923 * @param clk_id Clock ID according to tegra210 device tree binding
924 * Return: clock ID, or CLOCK_ID_NONE if the clock ID is invalid
925 */
926enum clock_id clk_id_to_pll_id(int clk_id)
927{
928 switch (clk_id) {
929 case TEGRA210_CLK_PLL_C:
930 return CLOCK_ID_CGENERAL;
931 case TEGRA210_CLK_PLL_M:
932 return CLOCK_ID_MEMORY;
933 case TEGRA210_CLK_PLL_P:
934 return CLOCK_ID_PERIPH;
935 case TEGRA210_CLK_PLL_A:
936 return CLOCK_ID_AUDIO;
937 case TEGRA210_CLK_PLL_U:
938 return CLOCK_ID_USB;
939 case TEGRA210_CLK_PLL_D:
940 case TEGRA210_CLK_PLL_D_OUT0:
941 return CLOCK_ID_DISPLAY;
942 case TEGRA210_CLK_PLL_X:
943 return CLOCK_ID_XCPU;
944 case TEGRA210_CLK_PLL_E:
945 return CLOCK_ID_EPCI;
946 case TEGRA210_CLK_CLK_32K:
947 return CLOCK_ID_32KHZ;
948 case TEGRA210_CLK_CLK_M:
949 return CLOCK_ID_CLK_M;
950 default:
951 return CLOCK_ID_NONE;
952 }
953}
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]954#endif /* CONFIG_OF_CONTROL */
955
956/*
957 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
958 * PLLP_BASE/MISC/etc. is already set up for 408MHz in the BootROM.
959 */
960void tegra210_setup_pllp(void)
961{
962 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
963 u32 reg;
964
965 /* Set PLLP_OUT1, 3 & 4 freqs to 9.6, 102 & 204MHz */
966
967 /* OUT1 */
968 /* Assert RSTN before enable */
969 reg = PLLP_OUT1_RSTN_EN;
970 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
971 /* Set divisor and reenable */
972 reg = (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
973 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
974 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
975
976 /* OUT3, 4 */
977 /* Assert RSTN before enable */
978 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
979 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
980 /* Set divisor and reenable */
981 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
982 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
983 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
984 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
985 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
986
987 /*
988 * NOTE: If you want to change PLLP_OUT2 away from 204MHz,
989 * you can change PLLP_BASE DIVP here. Currently defaults
990 * to 1, which is 2^1, or 2, so PLLP_OUT2 is 204MHz.
991 * See Table 13 in section 5.1.4 in T210 TRM for more info.
992 */
993}
994
995void clock_early_init(void)
996{
997 struct clk_rst_ctlr *clkrst =
998 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]999 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1000 u32 data;
1001
1002 tegra210_setup_pllp();
1003
1004 /*
1005 * PLLC output frequency set to 600Mhz
1006 * PLLD output frequency set to 925Mhz
1007 */
1008 switch (clock_get_osc_freq()) {
1009 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200[diff] [blame]1010 case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1011 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
1012 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
1013 break;
1014
1015 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
1016 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
1017 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
1018 break;
1019
1020 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
Svyatoslav Ryhel7f4ab332023-02-01 10:53:01 +0200[diff] [blame]1021 case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1022 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
1023 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
1024 break;
1025 case CLOCK_OSC_FREQ_19_2:
1026 clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0);
1027 clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12);
1028 break;
Tom Warren27bce712015-06-22 13:03:44 -0700[diff] [blame]1029 case CLOCK_OSC_FREQ_38_4:
1030 clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0);
1031 clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0);
1032 break;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1033 default:
1034 /*
1035 * These are not supported. It is too early to print a
1036 * message and the UART likely won't work anyway due to the
1037 * oscillator being wrong.
1038 */
1039 break;
1040 }
1041
1042 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */
1043 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,
1044 (1 << PLLC_IDDQ));
1045 udelay(2);
1046
1047 /*
1048 * PLLC_MISC: Take PLLC out of reset. NOTE: T210 PLLC_MISC maps
1049 * to pll_out[1]
1050 */
1051 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],
1052 (1 << PLLC_RESET));
1053 udelay(2);
1054
1055 /* PLLD_MISC: Set CLKENABLE and LOCK_DETECT bits */
Tom Warrena8480ef2015-06-25 09:50:44 -0700[diff] [blame]1056 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1057 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
1058 udelay(2);
1059}
1060
Thierry Redingfa6e24d2015-08-20 11:42:19 +0200[diff] [blame]1061unsigned int clk_m_get_rate(unsigned parent_rate)
1062{
1063 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1064 u32 value, div;
1065
1066 value = readl(&clkrst->crc_spare_reg0);
1067 div = ((value >> 2) & 0x3) + 1;
1068
1069 return parent_rate / div;
1070}
1071
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1072void arch_timer_init(void)
1073{
1074 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
1075 u32 freq, val;
1076
Thierry Reding4c3aaa72015-08-20 11:42:20 +0200[diff] [blame]1077 freq = clock_get_rate(CLOCK_ID_CLK_M);
1078 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1079
Thierry Reding4c3aaa72015-08-20 11:42:20 +0200[diff] [blame]1080 if (current_el() == 3)
1081 asm("msr cntfrq_el0, %0\n" : : "r" (freq));
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1082
1083 /* Only Tegra114+ has the System Counter regs */
1084 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
1085 writel(freq, &sysctr->cntfid0);
1086
1087 val = readl(&sysctr->cntcr);
1088 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
1089 writel(val, &sysctr->cntcr);
1090 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
1091}
1092
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1093#define PLLREFE_MISC 0x4c8
1094#define PLLREFE_MISC_LOCK BIT(27)
1095#define PLLREFE_MISC_IDDQ BIT(24)
1096
1097#define PLLREFE_BASE 0x4c4
1098#define PLLREFE_BASE_BYPASS BIT(31)
1099#define PLLREFE_BASE_ENABLE BIT(30)
1100#define PLLREFE_BASE_REF_DIS BIT(29)
1101#define PLLREFE_BASE_KCP(kcp) (((kcp) & 0x3) << 27)
1102#define PLLREFE_BASE_KVCO BIT(26)
1103#define PLLREFE_BASE_DIVP(p) (((p) & 0x1f) << 16)
1104#define PLLREFE_BASE_DIVN(n) (((n) & 0xff) << 8)
1105#define PLLREFE_BASE_DIVM(m) (((m) & 0xff) << 0)
1106
1107static int tegra_pllref_enable(void)
1108{
1109 u32 value;
1110 unsigned long start;
1111
1112 /*
1113 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1114 * Recovery Mode or Boot from USB", sub-section "PLLREFE".
1115 */
1116
1117 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1118 value &= ~PLLREFE_MISC_IDDQ;
1119 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1120
1121 udelay(5);
1122
1123 value = PLLREFE_BASE_ENABLE |
1124 PLLREFE_BASE_KCP(0) |
1125 PLLREFE_BASE_DIVP(0) |
1126 PLLREFE_BASE_DIVN(0x41) |
1127 PLLREFE_BASE_DIVM(4);
1128 writel(value, NV_PA_CLK_RST_BASE + PLLREFE_BASE);
1129
1130 debug("waiting for pllrefe lock\n");
1131 start = get_timer(0);
1132 while (get_timer(start) < 250) {
1133 value = readl(NV_PA_CLK_RST_BASE + PLLREFE_MISC);
1134 if (value & PLLREFE_MISC_LOCK)
1135 break;
1136 }
1137 if (!(value & PLLREFE_MISC_LOCK)) {
1138 debug(" timeout\n");
1139 return -ETIMEDOUT;
1140 }
1141 debug(" done\n");
1142
1143 return 0;
1144}
1145
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1146#define PLLE_SS_CNTL 0x68
1147#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
1148#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
1149#define PLLE_SS_CNTL_SSCINVERT (1 << 15)
1150#define PLLE_SS_CNTL_SSCCENTER (1 << 14)
1151#define PLLE_SS_CNTL_SSCBYP (1 << 12)
1152#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
1153#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
1154#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
1155
1156#define PLLE_BASE 0x0e8
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1157#define PLLE_BASE_ENABLE (1 << 31)
1158#define PLLE_BASE_PLDIV_CML(x) (((x) & 0x1f) << 24)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1159#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
1160#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
1161
1162#define PLLE_MISC 0x0ec
1163#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1164#define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
1165#define PLLE_MISC_LOCK (1 << 11)
Stephen Warrenb6409f22016-03-22 09:45:36 -0600[diff] [blame]1166#define PLLE_PTS (1 << 8)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1167#define PLLE_MISC_KCP(x) (((x) & 0x3) << 6)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1168#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1169#define PLLE_MISC_KVCO (1 << 0)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1170
1171#define PLLE_AUX 0x48c
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1172#define PLLE_AUX_SS_SEQ_INCLUDE (1 << 31)
1173#define PLLE_AUX_REF_SEL_PLLREFE (1 << 28)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1174#define PLLE_AUX_SEQ_ENABLE (1 << 24)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1175#define PLLE_AUX_SS_SWCTL (1 << 6)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1176#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1177#define PLLE_AUX_USE_LOCKDET (1 << 3)
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1178
1179int tegra_plle_enable(void)
1180{
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1181 u32 value;
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1182 unsigned long start;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1183
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1184 /* PLLREF feeds PLLE */
1185 tegra_pllref_enable();
1186
1187 /*
1188 * This sequence comes from Tegra X1 TRM section "Cold Boot, with no
1189 * Recovery Mode or Boot from USB", sub-section "PLLEs".
1190 */
1191
1192 /* 1. Select XTAL as the source */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1193
1194 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1195 value &= ~PLLE_AUX_REF_SEL_PLLREFE;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1196 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
1197
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1198 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1199 value &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1200 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
1201
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1202 /* 2. Wait 5 us */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1203 udelay(5);
1204
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1205 /*
1206 * 3. Program the following registers to generate a low jitter 100MHz
1207 * clock.
1208 */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1209
1210 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1211 value &= ~PLLE_BASE_PLDIV_CML(0x1f);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1212 value &= ~PLLE_BASE_NDIV(0xff);
1213 value &= ~PLLE_BASE_MDIV(0xff);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1214 value |= PLLE_BASE_PLDIV_CML(0xe);
1215 value |= PLLE_BASE_NDIV(0x7d);
1216 value |= PLLE_BASE_MDIV(2);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1217 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1218
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1219 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
Stephen Warrenb6409f22016-03-22 09:45:36 -0600[diff] [blame]1220 value |= PLLE_PTS;
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1221 value &= ~PLLE_MISC_KCP(3);
1222 value &= ~PLLE_MISC_VREG_CTRL(3);
1223 value &= ~PLLE_MISC_KVCO;
1224 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1225
1226 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1227 value |= PLLE_BASE_ENABLE;
1228 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1229
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1230 /* 4. Wait for LOCK */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1231
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1232 debug("waiting for plle lock\n");
1233 start = get_timer(0);
1234 while (get_timer(start) < 250) {
1235 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
1236 if (value & PLLE_MISC_LOCK)
1237 break;
1238 }
1239 if (!(value & PLLE_MISC_LOCK)) {
1240 debug(" timeout\n");
1241 return -ETIMEDOUT;
1242 }
1243 debug(" done\n");
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1244
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1245 /* 5. Enable SSA */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1246
1247 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1248 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
1249 value |= PLLE_SS_CNTL_SSCINC(1);
1250 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
1251 value |= PLLE_SS_CNTL_SSCINCINTR(0x23);
1252 value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff);
1253 value |= PLLE_SS_CNTL_SSCMAX(0x21);
1254 value &= ~PLLE_SS_CNTL_SSCINVERT;
1255 value &= ~PLLE_SS_CNTL_SSCCENTER;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1256 value &= ~PLLE_SS_CNTL_BYPASS_SS;
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1257 value &= ~PLLE_SS_CNTL_SSCBYP;
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1258 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1259
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1260 /* 6. Wait 300 ns */
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1261
Stephen Warren553b61e2015-10-05 16:58:52 -0600[diff] [blame]1262 udelay(1);
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1263 value &= ~PLLE_SS_CNTL_INTERP_RESET;
1264 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1265
Tom Warrenf80dd822015-02-02 13:22:29 -0700[diff] [blame]1266 return 0;
1267}
Stephen Warren1453d102016-09-13 10:45:55 -0600[diff] [blame]1268
Svyatoslav Ryhelc93b5182023-07-03 18:06:54 +0300[diff] [blame]1269struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
1270{
1271 struct clk_rst_ctlr *clkrst =
1272 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1273
1274 switch (clkid) {
1275 case CLOCK_ID_XCPU:
1276 case CLOCK_ID_EPCI:
1277 case CLOCK_ID_SFROM32KHZ:
1278 return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
1279 default:
1280 return NULL;
1281 }
1282}
1283
Stephen Warren1453d102016-09-13 10:45:55 -0600[diff] [blame]1284struct periph_clk_init periph_clk_init_table[] = {
1285 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
1286 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
1287 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
1288 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
1289 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
1290 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
1291 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
Stephen Warren1453d102016-09-13 10:45:55 -0600[diff] [blame]1292 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
1293 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
1294 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
1295 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
Svyatoslav Ryhelc226fc72023-02-14 19:35:28 +0200[diff] [blame]1296 { PERIPH_ID_PWM, CLOCK_ID_PERIPH },
Stephen Warren1453d102016-09-13 10:45:55 -0600[diff] [blame]1297 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
1298 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
1299 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
1300 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
1301 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
1302 { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
1303 { -1, },
1304};