Tom Rini | 8b0c8a1 | 2018-05-06 18:27:01 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
Patrick Delaunay | ba77940 | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 6 | #define LOG_CATEGORY LOGC_ARCH |
| 7 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 8 | #include <dm.h> |
Simon Glass | 2dc9c34 | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 9 | #include <image.h> |
| 10 | #include <init.h> |
Patrick Delaunay | d1633b3 | 2020-03-18 09:22:48 +0100 | [diff] [blame] | 11 | #include <lmb.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 13 | #include <ram.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 14 | #include <asm/global_data.h> |
Patrick Delaunay | c9b0dc3 | 2021-02-05 13:53:32 +0100 | [diff] [blame] | 15 | #include <asm/system.h> |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 16 | |
| 17 | DECLARE_GLOBAL_DATA_PTR; |
| 18 | |
| 19 | int dram_init(void) |
| 20 | { |
| 21 | struct ram_info ram; |
| 22 | struct udevice *dev; |
| 23 | int ret; |
| 24 | |
| 25 | ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
Patrice Chotard | 0f0faea | 2023-10-27 16:42:57 +0200 | [diff] [blame] | 26 | /* in case there is no RAM driver, retrieve DDR size from DT */ |
| 27 | if (ret == -ENODEV) { |
| 28 | return fdtdec_setup_mem_size_base(); |
| 29 | } else if (ret) { |
| 30 | log_err("RAM init failed: %d\n", ret); |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 31 | return ret; |
| 32 | } |
| 33 | ret = ram_get_info(dev, &ram); |
| 34 | if (ret) { |
Patrick Delaunay | ba77940 | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 35 | log_debug("Cannot get RAM size: %d\n", ret); |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 36 | return ret; |
| 37 | } |
Patrick Delaunay | 4c06377 | 2023-10-27 16:42:58 +0200 | [diff] [blame] | 38 | log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size); |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 39 | |
| 40 | gd->ram_size = ram.size; |
| 41 | |
| 42 | return 0; |
| 43 | } |
Patrick Delaunay | d1633b3 | 2020-03-18 09:22:48 +0100 | [diff] [blame] | 44 | |
Heinrich Schuchardt | 51a9aac | 2023-08-12 20:16:58 +0200 | [diff] [blame] | 45 | phys_addr_t board_get_usable_ram_top(phys_size_t total_size) |
Patrick Delaunay | d1633b3 | 2020-03-18 09:22:48 +0100 | [diff] [blame] | 46 | { |
Patrick Delaunay | c9b0dc3 | 2021-02-05 13:53:32 +0100 | [diff] [blame] | 47 | phys_size_t size; |
Patrick Delaunay | d1633b3 | 2020-03-18 09:22:48 +0100 | [diff] [blame] | 48 | phys_addr_t reg; |
| 49 | struct lmb lmb; |
| 50 | |
Patrick Delaunay | 9e249d8 | 2021-07-26 11:55:27 +0200 | [diff] [blame] | 51 | if (!total_size) |
Patrice Chotard | f9339b1 | 2021-09-01 09:56:02 +0200 | [diff] [blame] | 52 | return gd->ram_top; |
Patrick Delaunay | 9e249d8 | 2021-07-26 11:55:27 +0200 | [diff] [blame] | 53 | |
Patrice Chotard | 5501e38 | 2023-10-27 16:42:59 +0200 | [diff] [blame] | 54 | /* |
| 55 | * make sure U-Boot uses address space below 4GB boundaries even |
| 56 | * if the effective available memory is bigger |
| 57 | */ |
| 58 | gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); |
| 59 | |
Patrick Delaunay | d1633b3 | 2020-03-18 09:22:48 +0100 | [diff] [blame] | 60 | /* found enough not-reserved memory to relocated U-Boot */ |
| 61 | lmb_init(&lmb); |
Patrice Chotard | 5501e38 | 2023-10-27 16:42:59 +0200 | [diff] [blame] | 62 | lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base); |
Patrick Delaunay | d1633b3 | 2020-03-18 09:22:48 +0100 | [diff] [blame] | 63 | boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); |
Patrick Delaunay | f9203e9 | 2021-05-07 14:50:34 +0200 | [diff] [blame] | 64 | /* add 8M for reserved memory for display, fdt, gd,... */ |
| 65 | size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), |
Patrick Delaunay | c9b0dc3 | 2021-02-05 13:53:32 +0100 | [diff] [blame] | 66 | reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE); |
Patrick Delaunay | d1633b3 | 2020-03-18 09:22:48 +0100 | [diff] [blame] | 67 | |
Patrick Delaunay | c9b0dc3 | 2021-02-05 13:53:32 +0100 | [diff] [blame] | 68 | if (!reg) |
| 69 | reg = gd->ram_top - size; |
| 70 | |
Patrick Delaunay | f9203e9 | 2021-05-07 14:50:34 +0200 | [diff] [blame] | 71 | /* before relocation, mark the U-Boot memory as cacheable by default */ |
| 72 | if (!(gd->flags & GD_FLG_RELOC)) |
| 73 | mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); |
Patrick Delaunay | d1633b3 | 2020-03-18 09:22:48 +0100 | [diff] [blame] | 74 | |
Patrick Delaunay | c9b0dc3 | 2021-02-05 13:53:32 +0100 | [diff] [blame] | 75 | return reg + size; |
Patrick Delaunay | d1633b3 | 2020-03-18 09:22:48 +0100 | [diff] [blame] | 76 | } |