blob: 78b12fcbb6acafdca7ead328f8eb671a52297843 [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay85b53972018-03-12 10:46:10 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay85b53972018-03-12 10:46:10 +01004 */
5
Patrick Delaunayba779402020-11-06 19:01:29 +01006#define LOG_CATEGORY LOGC_ARCH
7
Patrick Delaunay85b53972018-03-12 10:46:10 +01008#include <dm.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06009#include <image.h>
10#include <init.h>
Patrick Delaunayd1633b32020-03-18 09:22:48 +010011#include <lmb.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Patrick Delaunay85b53972018-03-12 10:46:10 +010013#include <ram.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Patrick Delaunayc9b0dc32021-02-05 13:53:32 +010015#include <asm/system.h>
Patrick Delaunay85b53972018-03-12 10:46:10 +010016
17DECLARE_GLOBAL_DATA_PTR;
18
19int dram_init(void)
20{
21 struct ram_info ram;
22 struct udevice *dev;
23 int ret;
24
25 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
Patrice Chotard0f0faea2023-10-27 16:42:57 +020026 /* in case there is no RAM driver, retrieve DDR size from DT */
27 if (ret == -ENODEV) {
28 return fdtdec_setup_mem_size_base();
29 } else if (ret) {
30 log_err("RAM init failed: %d\n", ret);
Patrick Delaunay85b53972018-03-12 10:46:10 +010031 return ret;
32 }
33 ret = ram_get_info(dev, &ram);
34 if (ret) {
Patrick Delaunayba779402020-11-06 19:01:29 +010035 log_debug("Cannot get RAM size: %d\n", ret);
Patrick Delaunay85b53972018-03-12 10:46:10 +010036 return ret;
37 }
Patrick Delaunay4c063772023-10-27 16:42:58 +020038 log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
Patrick Delaunay85b53972018-03-12 10:46:10 +010039
40 gd->ram_size = ram.size;
41
42 return 0;
43}
Patrick Delaunayd1633b32020-03-18 09:22:48 +010044
Heinrich Schuchardt51a9aac2023-08-12 20:16:58 +020045phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
Patrick Delaunayd1633b32020-03-18 09:22:48 +010046{
Patrick Delaunayc9b0dc32021-02-05 13:53:32 +010047 phys_size_t size;
Patrick Delaunayd1633b32020-03-18 09:22:48 +010048 phys_addr_t reg;
49 struct lmb lmb;
50
Patrick Delaunay9e249d82021-07-26 11:55:27 +020051 if (!total_size)
Patrice Chotardf9339b12021-09-01 09:56:02 +020052 return gd->ram_top;
Patrick Delaunay9e249d82021-07-26 11:55:27 +020053
Patrice Chotard5501e382023-10-27 16:42:59 +020054 /*
55 * make sure U-Boot uses address space below 4GB boundaries even
56 * if the effective available memory is bigger
57 */
58 gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
59
Patrick Delaunayd1633b32020-03-18 09:22:48 +010060 /* found enough not-reserved memory to relocated U-Boot */
61 lmb_init(&lmb);
Patrice Chotard5501e382023-10-27 16:42:59 +020062 lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base);
Patrick Delaunayd1633b32020-03-18 09:22:48 +010063 boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
Patrick Delaunayf9203e92021-05-07 14:50:34 +020064 /* add 8M for reserved memory for display, fdt, gd,... */
65 size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
Patrick Delaunayc9b0dc32021-02-05 13:53:32 +010066 reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
Patrick Delaunayd1633b32020-03-18 09:22:48 +010067
Patrick Delaunayc9b0dc32021-02-05 13:53:32 +010068 if (!reg)
69 reg = gd->ram_top - size;
70
Patrick Delaunayf9203e92021-05-07 14:50:34 +020071 /* before relocation, mark the U-Boot memory as cacheable by default */
72 if (!(gd->flags & GD_FLG_RELOC))
73 mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
Patrick Delaunayd1633b32020-03-18 09:22:48 +010074
Patrick Delaunayc9b0dc32021-02-05 13:53:32 +010075 return reg + size;
Patrick Delaunayd1633b32020-03-18 09:22:48 +010076}