blob: f67fe166d31f09c8e9c800ad7894cadad4d7abb0 [file] [log] [blame]
Peng Fancbe5d382021-08-07 16:01:13 +08001// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
Gary Bisson4ed03c52024-08-05 23:25:11 +02006#include "imx8ulp-u-boot.dtsi"
7
Marcel Ziswiler4b61cbc2022-11-07 22:22:37 +01008/ {
9 mu@27020000 {
10 compatible = "fsl,imx8ulp-mu";
11 reg = <0 0x27020000 0 0x10000>;
12 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -070013 bootph-pre-ram;
Marcel Ziswiler4b61cbc2022-11-07 22:22:37 +010014 };
15};
16
17&soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -070018 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +080019};
20
21&per_bridge3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070022 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +080023};
24
25&per_bridge4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070026 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +080027};
28
29&iomuxc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070030 bootph-pre-ram;
Ye Li60f062a2023-01-18 17:31:15 +080031 fsl,mux_mask = <0xf00>;
Peng Fancbe5d382021-08-07 16:01:13 +080032};
33
34&pinctrl_lpuart5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070035 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +080036};
37
Peng Fancbe5d382021-08-07 16:01:13 +080038&lpuart5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070039 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +080040};
41
42&usdhc0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070043 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +080044};
45
46&pinctrl_usdhc0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070047 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +080048};