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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / arm / dts / imx8ulp-evk-u-boot.dtsi
blob: 608bde3a2a3bb5ce8b808d231d9eaa671cf5ab88 [file] [log] [blame]
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
Marcel Ziswiler4b61cbc2022-11-07 22:22:37 +0100[diff] [blame]6/ {
7 mu@27020000 {
8 compatible = "fsl,imx8ulp-mu";
9 reg = <0 0x27020000 0 0x10000>;
10 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]11 bootph-pre-ram;
Marcel Ziswiler4b61cbc2022-11-07 22:22:37 +0100[diff] [blame]12 };
13};
14
15&soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]16 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]17};
18
19&per_bridge3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]20 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]21};
22
23&per_bridge4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]24 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]25};
26
27&iomuxc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]28 bootph-pre-ram;
Ye Li60f062a2023-01-18 17:31:15 +0800[diff] [blame]29 fsl,mux_mask = <0xf00>;
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]30};
31
32&pinctrl_lpuart5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]33 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]34};
35
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]36&lpuart5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]37 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]38};
39
40&usdhc0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]41 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]42};
43
44&pinctrl_usdhc0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]45 bootph-pre-ram;
Peng Fancbe5d382021-08-07 16:01:13 +0800[diff] [blame]46};