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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / mips / dts / brcm,bcm6838.dtsi
blob: 4032e245286be0a3632785bcf63393fec327ba83 [file] [log] [blame]
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
4 */
5
6#include "skeleton.dtsi"
7
8/ {
9 compatible = "brcm,bcm6838";
10
11 cpus {
12 reg = <0x14e00000 0x4>;
13 #address-cells = <1>;
14 #size-cells = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]15 bootph-all;
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]16
17 cpu@0 {
18 compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
19 device_type = "cpu";
20 reg = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]21 bootph-all;
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]22 };
23
24 cpu@1 {
25 compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
26 device_type = "cpu";
27 reg = <1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]28 bootph-all;
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]29 };
30 };
31
32 clocks {
33 compatible = "simple-bus";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]34 bootph-all;
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]35
36 periph_osc: periph-osc {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <50000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]40 bootph-all;
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]41 };
42 };
43
44 ubus {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]48 bootph-all;
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]49
50 memory: memory-controller@12000000 {
51 compatible = "brcm,bcm6328-mc";
52 reg = <0x12000000 0x1000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]53 bootph-all;
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]54 };
55
Philippe Reynes72f1f4b2018-08-13 14:23:08 +0200[diff] [blame]56 gpio_test_port: syscon@14e00294 {
57 compatible = "syscon";
58 reg = <0x14e00294 0x1c>;
59 };
60
61 pinctrl: pinctrl {
62 compatible = "brcm,bcm6838-pinctrl";
63 regmap = <&gpio_test_port>;
64 brcm,pins-count = <74>;
65 brcm,functions-count = <8>;
66 };
67
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]68 uart0: serial@14e00500 {
69 compatible = "brcm,bcm6345-uart";
70 reg = <0x14e00500 0x18>;
71 clocks = <&periph_osc>;
72
73 status = "disabled";
74 };
75
Philippe Reynes24e954b2019-01-28 15:37:29 +0100[diff] [blame]76 wdt0: watchdog@14e002d0 {
77 compatible = "brcm,bcm6345-wdt";
78 reg = <0x14e002d0 0xc>;
79 clocks = <&periph_osc>;
80 };
81
82 wdt1: watchdog@14e002dc {
83 compatible = "brcm,bcm6345-wdt";
84 reg = <0x14e002dc 0xc>;
85 clocks = <&periph_osc>;
86 };
87
88 wdt-reboot {
89 compatible = "wdt-reboot";
90 wdt = <&wdt0>;
91 };
92
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]93 leds: led-controller@14e00f00 {
94 compatible = "brcm,bcm6328-leds";
95 reg = <0x14e00f00 0x28>;
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 status = "disabled";
100 };
Philippe Reynes44bfb862019-03-07 11:36:32 +0100[diff] [blame]101
102 gpio_lo: gpio-controller@14e00100 {
103 compatible = "brcm,bcm6345-gpio";
104 reg = <0x14e00100 0x4>, <0x14e0012c 0x4>;
105 gpio-controller;
106 #gpio-cells = <2>;
107
108 status = "disabled";
109 };
110
111 gpio_mid0: gpio-controller@14e00104 {
112 compatible = "brcm,bcm6345-gpio";
113 reg = <0x14e00104 0x4>, <0x14e00130 0x4>;
114 gpio-controller;
115 #gpio-cells = <2>;
116
117 status = "disabled";
118 };
119
120 gpio_mid1: gpio-controller@14e00108 {
121 compatible = "brcm,bcm6345-gpio";
122 reg = <0x14e00108 0x4>, <0x14e00134 0x4>;
123 gpio-controller;
124 #gpio-cells = <2>;
125
126 status = "disabled";
127 };
Philippe Reynes02edb4c2019-03-15 15:14:39 +0100[diff] [blame]128
129 nand: nand-controller@14e02200 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "brcm,nand-bcm6838",
133 "brcm,brcmnand-v5.0",
134 "brcm,brcmnand";
135 reg-names = "nand", "nand-int-base", "nand-cache";
136 reg = <0x14e02200 0x180>,
137 <0x14e000f0 0x10>,
138 <0x14e02600 0x180>;
139 status = "disabled";
140 };
Philippe Reynesd1406612018-07-16 19:06:14 +0200[diff] [blame]141 };
142};