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wdenk914be132004-06-08 00:22:43 +00001/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
wdenk914be132004-06-08 00:22:43 +000030 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
34#define CONFIG_OMAP 1 /* in a TI OMAP core */
35#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */
36#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */
37
Stefan Roese0df367f2006-05-10 10:55:16 +020038#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
39#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
40
wdenk914be132004-06-08 00:22:43 +000041/* input clock of PLL */
42/* the OMAP5912 OSK has 12MHz input clock */
43#define CONFIG_SYS_CLK_FREQ 12000000
44
45#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
46
47#define CONFIG_MISC_INIT_R
48
49#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
50#define CONFIG_SETUP_MEMORY_TAGS 1
Stefan Roese0df367f2006-05-10 10:55:16 +020051#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */
wdenk914be132004-06-08 00:22:43 +000052
53/*
54 * Size of malloc() pool
55 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
57#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk914be132004-06-08 00:22:43 +000058
59/*
60 * Hardware drivers
61 */
62/*
63*/
Nishanth Menonee1c20f2009-10-16 00:06:37 -050064#define CONFIG_NET_MULTI
65#define CONFIG_LAN91C96
wdenk914be132004-06-08 00:22:43 +000066#define CONFIG_LAN91C96_BASE 0x04800300
67#define CONFIG_LAN91C96_EXT_PHY
68
69/*
70 * NS16550 Configuration
71 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_NS16550
73#define CONFIG_SYS_NS16550_SERIAL
74#define CONFIG_SYS_NS16550_REG_SIZE (-4)
75#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
76#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
wdenk914be132004-06-08 00:22:43 +000077 on helen */
78
79/*
80 * select serial console configuration
81 */
82#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */
83
84/* allow to overwrite serial and ethaddr */
85#define CONFIG_ENV_OVERWRITE
86#define CONFIG_CONS_INDEX 1
87#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk914be132004-06-08 00:22:43 +000089
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -050090
91/*
92 * Command line configuration.
93 */
94#include <config_cmd_default.h>
95
96#define CONFIG_CMD_DHCP
97
98
Jon Loeligerc6d535a2007-07-09 21:57:31 -050099/*
100 * BOOTP options
101 */
102#define CONFIG_BOOTP_SUBNETMASK
103#define CONFIG_BOOTP_GATEWAY
104#define CONFIG_BOOTP_HOSTNAME
105#define CONFIG_BOOTP_BOOTPATH
106
wdenk914be132004-06-08 00:22:43 +0000107
wdenk914be132004-06-08 00:22:43 +0000108#include <configs/omap1510.h>
109
110#define CONFIG_BOOTDELAY 3
111#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \
112 root=/dev/nfs rw nfsroot=157.87.82.48:\
113 /home/mwd/myfs/target ip=dhcp"
114#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */
115#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */
116#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
117#define CONFIG_BOOTFILE "uImage" /* file to load */
118
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -0500119#if defined(CONFIG_CMD_KGDB)
wdenk914be132004-06-08 00:22:43 +0000120#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
121#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
122#endif
123
124/*
125 * Miscellaneous configurable options
126 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_LONGHELP /* undef to save memory */
128#define CONFIG_SYS_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */
129#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk914be132004-06-08 00:22:43 +0000130/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
132#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
133#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk914be132004-06-08 00:22:43 +0000134
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
136#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenk914be132004-06-08 00:22:43 +0000137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
wdenk914be132004-06-08 00:22:43 +0000139
140/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
141 * DPLL1. This time is further subdivided by a local divisor.
142 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
Ladislav Michl993e57d2009-03-30 18:58:41 +0200144#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
145#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
wdenk914be132004-06-08 00:22:43 +0000146
147/*-----------------------------------------------------------------------
148 * Stack sizes
149 *
150 * The stack sizes are set up in start.S using the settings below
151 */
152#define CONFIG_STACKSIZE (128*1024) /* regular stack */
153#ifdef CONFIG_USE_IRQ
154#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
155#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
156#endif
157
158/*-----------------------------------------------------------------------
159 * Physical Memory Map
160 */
161#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Stefan Roese0df367f2006-05-10 10:55:16 +0200162#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
wdenk914be132004-06-08 00:22:43 +0000163#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
164
Stefan Roese0df367f2006-05-10 10:55:16 +0200165#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
166#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
167
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenk914be132004-06-08 00:22:43 +0000169
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
wdenk914be132004-06-08 00:22:43 +0000171
172/*-----------------------------------------------------------------------
Stefan Roese0df367f2006-05-10 10:55:16 +0200173 * FLASH driver setup
wdenk914be132004-06-08 00:22:43 +0000174 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200176#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
Stefan Roese0df367f2006-05-10 10:55:16 +0200177
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
Stefan Roese0df367f2006-05-10 10:55:16 +0200179
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenk914be132004-06-08 00:22:43 +0000181#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
Stefan Roese0df367f2006-05-10 10:55:16 +0200183
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
185#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
Stefan Roese0df367f2006-05-10 10:55:16 +0200186
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200187#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk914be132004-06-08 00:22:43 +0000188
189/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
191#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk914be132004-06-08 00:22:43 +0000192
Stefan Roese0df367f2006-05-10 10:55:16 +0200193/*-----------------------------------------------------------------------
194 * FLASH and environment organization
195 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200196#define CONFIG_ENV_IS_IN_FLASH 1
Stefan Roese0df367f2006-05-10 10:55:16 +0200197/* addr of environment */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
Stefan Roese0df367f2006-05-10 10:55:16 +0200199
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200200#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
201#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
wdenk914be132004-06-08 00:22:43 +0000202
203#endif /* __CONFIG_H */