blob: 76132defc21c455804f199ae1285647548158646 [file] [log] [blame]
Peng Fan99878462019-08-27 06:25:51 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8#include <common.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Peng Fan99878462019-08-27 06:25:51 +000013#include <asm/io.h>
Peng Fan99878462019-08-27 06:25:51 +000014#include <div64.h>
15#include <errno.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Peng Fan99878462019-08-27 06:25:51 +000018
19DECLARE_GLOBAL_DATA_PTR;
20
21static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
22
Peng Fan4e36e332020-07-09 11:06:24 +080023static u32 get_root_clk(enum clk_root_index clock_id);
Ye Liebabd8d2021-03-25 17:30:17 +080024
25#ifdef CONFIG_IMX_HAB
26void hab_caam_clock_enable(unsigned char enable)
27{
28 /* The CAAM clock is always on for iMX8M */
29}
30#endif
31
Peng Fan99878462019-08-27 06:25:51 +000032void enable_ocotp_clk(unsigned char enable)
33{
Peng Fan60c29bb2019-12-30 16:52:30 +080034 clock_enable(CCGR_OCOTP, !!enable);
Peng Fan99878462019-08-27 06:25:51 +000035}
36
37int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
38{
Peng Fan60c29bb2019-12-30 16:52:30 +080039 /* 0 - 3 is valid i2c num */
40 if (i2c_num > 3)
41 return -EINVAL;
Peng Fan99878462019-08-27 06:25:51 +000042
Peng Fan60c29bb2019-12-30 16:52:30 +080043 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
Peng Fan99878462019-08-27 06:25:51 +000044
Peng Fan60c29bb2019-12-30 16:52:30 +080045 return 0;
Peng Fan99878462019-08-27 06:25:51 +000046}
47
48#ifdef CONFIG_SPL_BUILD
49static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
Peng Fand29bf222019-12-27 11:40:55 +080050 PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
Peng Fan99878462019-08-27 06:25:51 +000051 PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
52 PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
53 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
54 PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
55 PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
56 PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
Andrey Zhizhikin09786cd2021-05-03 09:59:17 +020057 PLL_1443X_RATE(266000000U, 400, 9, 2, 0),
Peng Fan99878462019-08-27 06:25:51 +000058 PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
59 PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
60};
61
Alifer Moraes39931102020-01-14 15:54:59 -030062static int fracpll_configure(enum pll_clocks pll, u32 freq)
Peng Fan99878462019-08-27 06:25:51 +000063{
64 int i;
65 u32 tmp, div_val;
66 void *pll_base;
67 struct imx_int_pll_rate_table *rate;
68
69 for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
70 if (freq == imx8mm_fracpll_tbl[i].rate)
71 break;
72 }
73
74 if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
Andrey Zhizhikin367ca322021-05-03 10:02:10 +020075 printf("%s: No matched freq table %u\n", __func__, freq);
Peng Fan99878462019-08-27 06:25:51 +000076 return -EINVAL;
77 }
78
79 rate = &imx8mm_fracpll_tbl[i];
80
81 switch (pll) {
82 case ANATOP_DRAM_PLL:
83 setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
84 setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
85 writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
86
87 pll_base = &ana_pll->dram_pll_gnrl_ctl;
88 break;
89 case ANATOP_VIDEO_PLL:
90 pll_base = &ana_pll->video_pll1_gnrl_ctl;
91 break;
92 default:
93 return 0;
94 }
95 /* Bypass clock and set lock to pll output lock */
96 tmp = readl(pll_base);
97 tmp |= BYPASS_MASK;
98 writel(tmp, pll_base);
99
100 /* Enable RST */
101 tmp &= ~RST_MASK;
102 writel(tmp, pll_base);
103
104 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
105 (rate->sdiv << SDIV_SHIFT);
106 writel(div_val, pll_base + 4);
107 writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
108
109 __udelay(100);
110
111 /* Disable RST */
112 tmp |= RST_MASK;
113 writel(tmp, pll_base);
114
115 /* Wait Lock*/
116 while (!(readl(pll_base) & LOCK_STATUS))
117 ;
118
119 /* Bypass */
120 tmp &= ~BYPASS_MASK;
121 writel(tmp, pll_base);
122
123 return 0;
124}
125
126void dram_pll_init(ulong pll_val)
127{
128 fracpll_configure(ANATOP_DRAM_PLL, pll_val);
129}
130
131static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
132 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
133 CLK_ROOT_PRE_DIV2),
134 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
135 CLK_ROOT_PRE_DIV2),
136 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
137 CLK_ROOT_PRE_DIV2),
138};
139
140void dram_enable_bypass(ulong clk_val)
141{
142 int i;
143 struct dram_bypass_clk_setting *config;
144
145 for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
146 if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
147 break;
148 }
149
150 if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
Andrey Zhizhikin367ca322021-05-03 10:02:10 +0200151 printf("%s: No matched freq table %lu\n", __func__, clk_val);
Peng Fan99878462019-08-27 06:25:51 +0000152 return;
153 }
154
155 config = &imx8mm_dram_bypass_tbl[i];
156
157 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
158 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
159 CLK_ROOT_PRE_DIV(config->alt_pre_div));
160 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
161 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
162 CLK_ROOT_PRE_DIV(config->apb_pre_div));
163 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
164 CLK_ROOT_SOURCE_SEL(1));
165}
166
167void dram_disable_bypass(void)
168{
169 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
170 CLK_ROOT_SOURCE_SEL(0));
171 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
172 CLK_ROOT_SOURCE_SEL(4) |
173 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
174}
175#endif
176
Peng Fan4e36e332020-07-09 11:06:24 +0800177int intpll_configure(enum pll_clocks pll, ulong freq)
178{
179 void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
180 u32 pll_div_ctl_val, pll_clke_masks;
181
182 switch (pll) {
183 case ANATOP_SYSTEM_PLL1:
184 pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl;
185 pll_div_ctl = &ana_pll->sys_pll1_div_ctl;
186 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
187 INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
188 INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
189 INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
190 INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
191 break;
192 case ANATOP_SYSTEM_PLL2:
193 pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl;
194 pll_div_ctl = &ana_pll->sys_pll2_div_ctl;
195 pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
196 INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
197 INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
198 INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
199 INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
200 break;
201 case ANATOP_SYSTEM_PLL3:
202 pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl;
203 pll_div_ctl = &ana_pll->sys_pll3_div_ctl;
204 pll_clke_masks = INTPLL_CLKE_MASK;
205 break;
206 case ANATOP_ARM_PLL:
207 pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl;
208 pll_div_ctl = &ana_pll->arm_pll_div_ctl;
209 pll_clke_masks = INTPLL_CLKE_MASK;
210 break;
211 case ANATOP_GPU_PLL:
212 pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl;
213 pll_div_ctl = &ana_pll->gpu_pll_div_ctl;
214 pll_clke_masks = INTPLL_CLKE_MASK;
215 break;
216 case ANATOP_VPU_PLL:
217 pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl;
218 pll_div_ctl = &ana_pll->vpu_pll_div_ctl;
219 pll_clke_masks = INTPLL_CLKE_MASK;
220 break;
221 default:
222 return -EINVAL;
223 };
224
225 switch (freq) {
226 case MHZ(600):
227 /* 24 * 0x12c / 3 / 2 ^ 2 */
228 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
229 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
230 break;
231 case MHZ(750):
232 /* 24 * 0xfa / 2 / 2 ^ 2 */
233 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
234 INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2);
235 break;
236 case MHZ(800):
237 /* 24 * 0x190 / 3 / 2 ^ 2 */
238 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
239 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
240 break;
241 case MHZ(1000):
242 /* 24 * 0xfa / 3 / 2 ^ 1 */
243 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
244 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
245 break;
246 case MHZ(1200):
Marek Vasutd2578f22022-01-25 03:48:05 +0100247 /* 24 * 0x12c / 3 / 2 ^ 1 */
248 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) |
249 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
Peng Fan4e36e332020-07-09 11:06:24 +0800250 break;
Marek Vasutd376a502022-01-25 03:48:06 +0100251 case MHZ(1400):
252 /* 24 * 0x15e / 3 / 2 ^ 1 */
253 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x15e) |
254 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
255 break;
256 case MHZ(1500):
257 /* 24 * 0x177 / 3 / 2 ^ 1 */
258 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x177) |
259 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
260 break;
261 case MHZ(1600):
262 /* 24 * 0xc8 / 3 / 2 ^ 0 */
263 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
264 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
265 break;
266 case MHZ(1800):
267 /* 24 * 0xe1 / 3 / 2 ^ 0 */
268 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xe1) |
269 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
270 break;
Peng Fan4e36e332020-07-09 11:06:24 +0800271 case MHZ(2000):
272 /* 24 * 0xfa / 3 / 2 ^ 0 */
273 pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
274 INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
275 break;
276 default:
277 return -EINVAL;
278 };
279 /* Bypass clock and set lock to pll output lock */
280 setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK);
281 /* Enable reset */
282 clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
283 /* Configure */
284 writel(pll_div_ctl_val, pll_div_ctl);
285
286 __udelay(100);
287
288 /* Disable reset */
289 setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
290 /* Wait Lock */
291 while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
292 ;
293 /* Clear bypass */
294 clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
295 setbits_le32(pll_gnrl_ctl, pll_clke_masks);
296
297 return 0;
298}
299
Peng Fan99878462019-08-27 06:25:51 +0000300void init_uart_clk(u32 index)
301{
302 /*
303 * set uart clock root
304 * 24M OSC
305 */
306 switch (index) {
307 case 0:
308 clock_enable(CCGR_UART1, 0);
309 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
310 CLK_ROOT_SOURCE_SEL(0));
311 clock_enable(CCGR_UART1, 1);
312 return;
313 case 1:
314 clock_enable(CCGR_UART2, 0);
315 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
316 CLK_ROOT_SOURCE_SEL(0));
317 clock_enable(CCGR_UART2, 1);
318 return;
319 case 2:
320 clock_enable(CCGR_UART3, 0);
321 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
322 CLK_ROOT_SOURCE_SEL(0));
323 clock_enable(CCGR_UART3, 1);
324 return;
325 case 3:
326 clock_enable(CCGR_UART4, 0);
327 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
328 CLK_ROOT_SOURCE_SEL(0));
329 clock_enable(CCGR_UART4, 1);
330 return;
331 default:
332 printf("Invalid uart index\n");
333 return;
334 }
335}
336
337void init_wdog_clk(void)
338{
339 clock_enable(CCGR_WDOG1, 0);
340 clock_enable(CCGR_WDOG2, 0);
341 clock_enable(CCGR_WDOG3, 0);
342 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
343 CLK_ROOT_SOURCE_SEL(0));
344 clock_enable(CCGR_WDOG1, 1);
345 clock_enable(CCGR_WDOG2, 1);
346 clock_enable(CCGR_WDOG3, 1);
347}
348
Peng Fanc61ec9b2020-07-09 11:35:15 +0800349void init_clk_usdhc(u32 index)
350{
351 /*
352 * set usdhc clock root
353 * sys pll1 400M
354 */
355 switch (index) {
356 case 0:
357 clock_enable(CCGR_USDHC1, 0);
358 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
359 CLK_ROOT_SOURCE_SEL(1));
360 clock_enable(CCGR_USDHC1, 1);
361 return;
362 case 1:
363 clock_enable(CCGR_USDHC2, 0);
364 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
365 CLK_ROOT_SOURCE_SEL(1));
366 clock_enable(CCGR_USDHC2, 1);
367 return;
368 case 2:
369 clock_enable(CCGR_USDHC3, 0);
370 clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
371 CLK_ROOT_SOURCE_SEL(1));
372 clock_enable(CCGR_USDHC3, 1);
373 return;
374 default:
375 printf("Invalid usdhc index\n");
376 return;
377 }
378}
379
380void init_clk_ecspi(u32 index)
381{
382 switch (index) {
383 case 0:
384 clock_enable(CCGR_ECSPI1, 0);
385 clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
386 clock_enable(CCGR_ECSPI1, 1);
387 return;
388 case 1:
389 clock_enable(CCGR_ECSPI2, 0);
390 clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
391 clock_enable(CCGR_ECSPI2, 1);
Peng Fan016c2512020-09-16 15:17:21 +0800392 return;
Peng Fanc61ec9b2020-07-09 11:35:15 +0800393 case 2:
394 clock_enable(CCGR_ECSPI3, 0);
395 clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
396 clock_enable(CCGR_ECSPI3, 1);
397 return;
398 default:
399 printf("Invalid ecspi index\n");
400 return;
401 }
402}
403
404void init_nand_clk(void)
405{
406 /*
407 * set rawnand root
408 * sys pll1 400M
409 */
410 clock_enable(CCGR_RAWNAND, 0);
411 clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
412 CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
413 clock_enable(CCGR_RAWNAND, 1);
414}
415
Peng Fan99878462019-08-27 06:25:51 +0000416int clock_init(void)
417{
418 u32 val_cfg0;
419
420 /*
421 * The gate is not exported to clk tree, so configure them here.
422 * According to ANAMIX SPEC
423 * sys pll1 fixed at 800MHz
424 * sys pll2 fixed at 1GHz
425 * Here we only enable the outputs.
426 */
427 val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
428 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
429 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
430 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
431 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
432 INTPLL_DIV20_CLKE_MASK;
433 writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
434
435 val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
436 val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
437 INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
438 INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
439 INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
440 INTPLL_DIV20_CLKE_MASK;
441 writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
442
Peng Fan4e36e332020-07-09 11:06:24 +0800443 /* Configure ARM at 1.2GHz */
444 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
445 CLK_ROOT_SOURCE_SEL(2));
446
447 intpll_configure(ANATOP_ARM_PLL, MHZ(1200));
448
449 /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
450 clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
451
Peng Fane5653932020-07-09 11:18:50 +0800452 if (is_imx8mn() || is_imx8mp())
453 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(600));
454 else
455 intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
456
457#ifdef CONFIG_IMX8MP
458 /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */
459 /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */
460 clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
461#else
462 clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));
463
Peng Fan99878462019-08-27 06:25:51 +0000464 /* config GIC to sys_pll2_100m */
465 clock_enable(CCGR_GIC, 0);
466 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
467 CLK_ROOT_SOURCE_SEL(3));
468 clock_enable(CCGR_GIC, 1);
Peng Fane5653932020-07-09 11:18:50 +0800469#endif
Peng Fan99878462019-08-27 06:25:51 +0000470
471 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
472 CLK_ROOT_SOURCE_SEL(1));
473
474 clock_enable(CCGR_DDR1, 0);
475 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
476 CLK_ROOT_SOURCE_SEL(1));
477 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
478 CLK_ROOT_SOURCE_SEL(1));
479 clock_enable(CCGR_DDR1, 1);
480
481 init_wdog_clk();
482
483 clock_enable(CCGR_TEMP_SENSOR, 1);
484
485 clock_enable(CCGR_SEC_DEBUG, 1);
486
487 return 0;
488};
489
490u32 imx_get_uartclk(void)
491{
492 return 24000000U;
493}
494
Alifer Moraes39931102020-01-14 15:54:59 -0300495static u32 decode_intpll(enum clk_root_src intpll)
Peng Fan60c29bb2019-12-30 16:52:30 +0800496{
497 u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
498 u32 main_div, pre_div, post_div, div;
499 u64 freq;
500
501 switch (intpll) {
502 case ARM_PLL_CLK:
503 pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
504 pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
505 break;
506 case GPU_PLL_CLK:
507 pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
508 pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
509 break;
510 case VPU_PLL_CLK:
511 pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
512 pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
513 break;
514 case SYSTEM_PLL1_800M_CLK:
515 case SYSTEM_PLL1_400M_CLK:
516 case SYSTEM_PLL1_266M_CLK:
517 case SYSTEM_PLL1_200M_CLK:
518 case SYSTEM_PLL1_160M_CLK:
519 case SYSTEM_PLL1_133M_CLK:
520 case SYSTEM_PLL1_100M_CLK:
521 case SYSTEM_PLL1_80M_CLK:
522 case SYSTEM_PLL1_40M_CLK:
523 pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
524 pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
525 break;
526 case SYSTEM_PLL2_1000M_CLK:
527 case SYSTEM_PLL2_500M_CLK:
528 case SYSTEM_PLL2_333M_CLK:
529 case SYSTEM_PLL2_250M_CLK:
530 case SYSTEM_PLL2_200M_CLK:
531 case SYSTEM_PLL2_166M_CLK:
532 case SYSTEM_PLL2_125M_CLK:
533 case SYSTEM_PLL2_100M_CLK:
534 case SYSTEM_PLL2_50M_CLK:
535 pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
536 pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
537 break;
538 case SYSTEM_PLL3_CLK:
539 pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
540 pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
541 break;
542 default:
543 return -EINVAL;
544 }
545
546 /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
547 if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
548 return 0;
549
550 if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
551 return 0;
552
553 /*
554 * When BYPASS is equal to 1, PLL enters the bypass mode
555 * regardless of the values of RESETB
556 */
557 if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
558 return 24000000u;
559
560 if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
561 puts("pll not locked\n");
562 return 0;
563 }
564
565 switch (intpll) {
566 case ARM_PLL_CLK:
567 case GPU_PLL_CLK:
568 case VPU_PLL_CLK:
569 case SYSTEM_PLL3_CLK:
570 case SYSTEM_PLL1_800M_CLK:
571 case SYSTEM_PLL2_1000M_CLK:
572 pll_clke_mask = INTPLL_CLKE_MASK;
573 div = 1;
574 break;
575
576 case SYSTEM_PLL1_400M_CLK:
577 case SYSTEM_PLL2_500M_CLK:
578 pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
579 div = 2;
580 break;
581
582 case SYSTEM_PLL1_266M_CLK:
583 case SYSTEM_PLL2_333M_CLK:
584 pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
585 div = 3;
586 break;
587
588 case SYSTEM_PLL1_200M_CLK:
589 case SYSTEM_PLL2_250M_CLK:
590 pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
591 div = 4;
592 break;
593
594 case SYSTEM_PLL1_160M_CLK:
595 case SYSTEM_PLL2_200M_CLK:
596 pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
597 div = 5;
598 break;
599
600 case SYSTEM_PLL1_133M_CLK:
601 case SYSTEM_PLL2_166M_CLK:
602 pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
603 div = 6;
604 break;
605
606 case SYSTEM_PLL1_100M_CLK:
607 case SYSTEM_PLL2_125M_CLK:
608 pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
609 div = 8;
610 break;
611
612 case SYSTEM_PLL1_80M_CLK:
613 case SYSTEM_PLL2_100M_CLK:
614 pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
615 div = 10;
616 break;
617
618 case SYSTEM_PLL1_40M_CLK:
619 case SYSTEM_PLL2_50M_CLK:
620 pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
621 div = 20;
622 break;
623 default:
624 return -EINVAL;
625 }
626
627 if ((pll_gnrl_ctl & pll_clke_mask) == 0)
628 return 0;
629
630 main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
631 INTPLL_MAIN_DIV_SHIFT;
632 pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
633 INTPLL_PRE_DIV_SHIFT;
634 post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
635 INTPLL_POST_DIV_SHIFT;
636
637 /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
638 freq = 24000000ULL * main_div;
639 return lldiv(freq, pre_div * (1 << post_div) * div);
640}
641
Alifer Moraes39931102020-01-14 15:54:59 -0300642static u32 decode_fracpll(enum clk_root_src frac_pll)
Peng Fan60c29bb2019-12-30 16:52:30 +0800643{
644 u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
645 u32 main_div, pre_div, post_div, k;
646
647 switch (frac_pll) {
648 case DRAM_PLL1_CLK:
649 pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
650 pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
651 pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
652 break;
653 case AUDIO_PLL1_CLK:
654 pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
655 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
656 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
657 break;
658 case AUDIO_PLL2_CLK:
659 pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
660 pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
661 pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
662 break;
663 case VIDEO_PLL_CLK:
664 pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
665 pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
666 pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
667 break;
668 default:
Andrey Zhizhikin367ca322021-05-03 10:02:10 +0200669 printf("Unsupported clk_root_src %d\n", frac_pll);
Peng Fan60c29bb2019-12-30 16:52:30 +0800670 return 0;
671 }
672
673 /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
Ye Licc643ea2020-03-23 19:54:29 -0700674 if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
Peng Fan60c29bb2019-12-30 16:52:30 +0800675 return 0;
676
Ye Licc643ea2020-03-23 19:54:29 -0700677 if ((pll_gnrl_ctl & RST_MASK) == 0)
Peng Fan60c29bb2019-12-30 16:52:30 +0800678 return 0;
679 /*
680 * When BYPASS is equal to 1, PLL enters the bypass mode
681 * regardless of the values of RESETB
682 */
Ye Licc643ea2020-03-23 19:54:29 -0700683 if (pll_gnrl_ctl & BYPASS_MASK)
Peng Fan60c29bb2019-12-30 16:52:30 +0800684 return 24000000u;
685
Ye Licc643ea2020-03-23 19:54:29 -0700686 if (!(pll_gnrl_ctl & LOCK_STATUS)) {
Peng Fan60c29bb2019-12-30 16:52:30 +0800687 puts("pll not locked\n");
688 return 0;
689 }
690
Ye Licc643ea2020-03-23 19:54:29 -0700691 if (!(pll_gnrl_ctl & CLKE_MASK))
Peng Fan60c29bb2019-12-30 16:52:30 +0800692 return 0;
693
Ye Licc643ea2020-03-23 19:54:29 -0700694 main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
695 MDIV_SHIFT;
696 pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
697 PDIV_SHIFT;
698 post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
699 SDIV_SHIFT;
Peng Fan60c29bb2019-12-30 16:52:30 +0800700
Ye Licc643ea2020-03-23 19:54:29 -0700701 k = pll_fdiv_ctl1 & KDIV_MASK;
Peng Fan60c29bb2019-12-30 16:52:30 +0800702
703 return lldiv((main_div * 65536 + k) * 24000000ULL,
704 65536 * pre_div * (1 << post_div));
705}
706
Alifer Moraes39931102020-01-14 15:54:59 -0300707static u32 get_root_src_clk(enum clk_root_src root_src)
Peng Fan60c29bb2019-12-30 16:52:30 +0800708{
709 switch (root_src) {
710 case OSC_24M_CLK:
711 return 24000000u;
712 case OSC_HDMI_CLK:
713 return 26000000u;
714 case OSC_32K_CLK:
715 return 32000u;
716 case ARM_PLL_CLK:
717 case GPU_PLL_CLK:
718 case VPU_PLL_CLK:
719 case SYSTEM_PLL1_800M_CLK:
720 case SYSTEM_PLL1_400M_CLK:
721 case SYSTEM_PLL1_266M_CLK:
722 case SYSTEM_PLL1_200M_CLK:
723 case SYSTEM_PLL1_160M_CLK:
724 case SYSTEM_PLL1_133M_CLK:
725 case SYSTEM_PLL1_100M_CLK:
726 case SYSTEM_PLL1_80M_CLK:
727 case SYSTEM_PLL1_40M_CLK:
728 case SYSTEM_PLL2_1000M_CLK:
729 case SYSTEM_PLL2_500M_CLK:
730 case SYSTEM_PLL2_333M_CLK:
731 case SYSTEM_PLL2_250M_CLK:
732 case SYSTEM_PLL2_200M_CLK:
733 case SYSTEM_PLL2_166M_CLK:
734 case SYSTEM_PLL2_125M_CLK:
735 case SYSTEM_PLL2_100M_CLK:
736 case SYSTEM_PLL2_50M_CLK:
737 case SYSTEM_PLL3_CLK:
738 return decode_intpll(root_src);
739 case DRAM_PLL1_CLK:
740 case AUDIO_PLL1_CLK:
741 case AUDIO_PLL2_CLK:
742 case VIDEO_PLL_CLK:
743 return decode_fracpll(root_src);
Peng Fan4e36e332020-07-09 11:06:24 +0800744 case ARM_A53_ALT_CLK:
745 return get_root_clk(ARM_A53_CLK_ROOT);
Peng Fan60c29bb2019-12-30 16:52:30 +0800746 default:
747 return 0;
748 }
749
750 return 0;
751}
752
Alifer Moraes39931102020-01-14 15:54:59 -0300753static u32 get_root_clk(enum clk_root_index clock_id)
Peng Fan60c29bb2019-12-30 16:52:30 +0800754{
755 enum clk_root_src root_src;
756 u32 post_podf, pre_podf, root_src_clk;
757
758 if (clock_root_enabled(clock_id) <= 0)
759 return 0;
760
761 if (clock_get_prediv(clock_id, &pre_podf) < 0)
762 return 0;
763
764 if (clock_get_postdiv(clock_id, &post_podf) < 0)
765 return 0;
766
767 if (clock_get_src(clock_id, &root_src) < 0)
768 return 0;
769
770 root_src_clk = get_root_src_clk(root_src);
771
772 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
773}
774
Peng Fan4e36e332020-07-09 11:06:24 +0800775u32 get_arm_core_clk(void)
776{
777 enum clk_root_src root_src;
778 u32 root_src_clk;
779
780 if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
781 return 0;
782
783 root_src_clk = get_root_src_clk(root_src);
784
785 return root_src_clk;
786}
787
Peng Fan99878462019-08-27 06:25:51 +0000788u32 mxc_get_clock(enum mxc_clock clk)
789{
Peng Fan60c29bb2019-12-30 16:52:30 +0800790 u32 val;
Peng Fan99878462019-08-27 06:25:51 +0000791
792 switch (clk) {
Peng Fan99878462019-08-27 06:25:51 +0000793 case MXC_ARM_CLK:
Peng Fan4e36e332020-07-09 11:06:24 +0800794 return get_arm_core_clk();
Peng Fan60c29bb2019-12-30 16:52:30 +0800795 case MXC_IPG_CLK:
796 clock_get_target_val(IPG_CLK_ROOT, &val);
797 val = val & 0x3;
798 return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
799 case MXC_CSPI_CLK:
800 return get_root_clk(ECSPI1_CLK_ROOT);
801 case MXC_ESDHC_CLK:
802 return get_root_clk(USDHC1_CLK_ROOT);
803 case MXC_ESDHC2_CLK:
804 return get_root_clk(USDHC2_CLK_ROOT);
805 case MXC_ESDHC3_CLK:
806 return get_root_clk(USDHC3_CLK_ROOT);
807 case MXC_I2C_CLK:
808 return get_root_clk(I2C1_CLK_ROOT);
809 case MXC_UART_CLK:
810 return get_root_clk(UART1_CLK_ROOT);
811 case MXC_QSPI_CLK:
812 return get_root_clk(QSPI_CLK_ROOT);
Peng Fan99878462019-08-27 06:25:51 +0000813 default:
Peng Fan60c29bb2019-12-30 16:52:30 +0800814 printf("Unsupported mxc_clock %d\n", clk);
815 break;
Peng Fan99878462019-08-27 06:25:51 +0000816 }
817
818 return 0;
819}
Marek Vasut363725d2020-04-24 21:37:26 +0200820
Peng Fan1dd259c2020-07-09 13:14:20 +0800821#ifdef CONFIG_DWC_ETH_QOS
822int set_clk_eqos(enum enet_freq type)
823{
824 u32 target;
825 u32 enet1_ref;
826
827 switch (type) {
828 case ENET_125MHZ:
829 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
830 break;
831 case ENET_50MHZ:
832 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
833 break;
834 case ENET_25MHZ:
835 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
836 break;
837 default:
838 return -EINVAL;
839 }
840
841 /* disable the clock first */
842 clock_enable(CCGR_QOS_ETHENET, 0);
843 clock_enable(CCGR_SDMA2, 0);
844
845 /* set enet axi clock 266Mhz */
846 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
847 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
848 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
849 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
850
851 target = CLK_ROOT_ON | enet1_ref |
852 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
853 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
854 clock_set_target_val(ENET_QOS_CLK_ROOT, target);
855
856 target = CLK_ROOT_ON |
857 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
858 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
859 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
860 clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
861
862 /* enable clock */
863 clock_enable(CCGR_QOS_ETHENET, 1);
864 clock_enable(CCGR_SDMA2, 1);
865
866 return 0;
867}
868
Marek BehĂșn789a99e2021-05-20 13:24:16 +0200869int imx_eqos_txclk_set_rate(ulong rate)
Peng Fan1dd259c2020-07-09 13:14:20 +0800870{
871 u32 val;
872 u32 eqos_post_div;
873
874 /* disable the clock first */
875 clock_enable(CCGR_QOS_ETHENET, 0);
876 clock_enable(CCGR_SDMA2, 0);
877
878 switch (rate) {
879 case 125000000:
880 eqos_post_div = 1;
881 break;
882 case 25000000:
883 eqos_post_div = 125000000 / 25000000;
884 break;
885 case 2500000:
886 eqos_post_div = 125000000 / 2500000;
887 break;
888 default:
889 return -EINVAL;
890 }
891
892 clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
893 val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
894 val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
895 CLK_ROOT_POST_DIV(eqos_post_div - 1);
896 clock_set_target_val(ENET_QOS_CLK_ROOT, val);
897
898 /* enable clock */
899 clock_enable(CCGR_QOS_ETHENET, 1);
900 clock_enable(CCGR_SDMA2, 1);
901
902 return 0;
903}
904
905u32 imx_get_eqos_csr_clk(void)
906{
907 return get_root_clk(ENET_AXI_CLK_ROOT);
908}
909#endif
910
Marek Vasut363725d2020-04-24 21:37:26 +0200911#ifdef CONFIG_FEC_MXC
912int set_clk_enet(enum enet_freq type)
913{
914 u32 target;
915 u32 enet1_ref;
916
917 switch (type) {
918 case ENET_125MHZ:
919 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
920 break;
921 case ENET_50MHZ:
922 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
923 break;
924 case ENET_25MHZ:
925 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
926 break;
927 default:
928 return -EINVAL;
929 }
930
931 /* disable the clock first */
932 clock_enable(CCGR_ENET1, 0);
933 clock_enable(CCGR_SIM_ENET, 0);
934
935 /* set enet axi clock 266Mhz */
936 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
937 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
938 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
939 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
940
941 target = CLK_ROOT_ON | enet1_ref |
942 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
943 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
944 clock_set_target_val(ENET_REF_CLK_ROOT, target);
945
946 target = CLK_ROOT_ON |
947 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
948 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
949 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
950 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
951
952 /* enable clock */
953 clock_enable(CCGR_SIM_ENET, 1);
954 clock_enable(CCGR_ENET1, 1);
955
956 return 0;
957}
958#endif