Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2018-2019 NXP |
| 4 | * |
| 5 | * Peng Fan <peng.fan@nxp.com> |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/arch/clock.h> |
| 10 | #include <asm/arch/imx-regs.h> |
| 11 | #include <asm/arch/sys_proto.h> |
| 12 | #include <asm/io.h> |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 13 | #include <div64.h> |
| 14 | #include <errno.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 15 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 16 | #include <linux/delay.h> |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
| 20 | static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; |
| 21 | |
Peng Fan | 4e36e33 | 2020-07-09 11:06:24 +0800 | [diff] [blame] | 22 | static u32 get_root_clk(enum clk_root_index clock_id); |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 23 | void enable_ocotp_clk(unsigned char enable) |
| 24 | { |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 25 | clock_enable(CCGR_OCOTP, !!enable); |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 26 | } |
| 27 | |
| 28 | int enable_i2c_clk(unsigned char enable, unsigned i2c_num) |
| 29 | { |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 30 | /* 0 - 3 is valid i2c num */ |
| 31 | if (i2c_num > 3) |
| 32 | return -EINVAL; |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 33 | |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 34 | clock_enable(CCGR_I2C1 + i2c_num, !!enable); |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 35 | |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 36 | return 0; |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 37 | } |
| 38 | |
| 39 | #ifdef CONFIG_SPL_BUILD |
| 40 | static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { |
Peng Fan | d29bf22 | 2019-12-27 11:40:55 +0800 | [diff] [blame] | 41 | PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 42 | PLL_1443X_RATE(800000000U, 300, 9, 0, 0), |
| 43 | PLL_1443X_RATE(750000000U, 250, 8, 0, 0), |
| 44 | PLL_1443X_RATE(650000000U, 325, 3, 2, 0), |
| 45 | PLL_1443X_RATE(600000000U, 300, 3, 2, 0), |
| 46 | PLL_1443X_RATE(594000000U, 99, 1, 2, 0), |
| 47 | PLL_1443X_RATE(400000000U, 300, 9, 1, 0), |
| 48 | PLL_1443X_RATE(266666667U, 400, 9, 2, 0), |
| 49 | PLL_1443X_RATE(167000000U, 334, 3, 4, 0), |
| 50 | PLL_1443X_RATE(100000000U, 300, 9, 3, 0), |
| 51 | }; |
| 52 | |
Alifer Moraes | 3993110 | 2020-01-14 15:54:59 -0300 | [diff] [blame] | 53 | static int fracpll_configure(enum pll_clocks pll, u32 freq) |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 54 | { |
| 55 | int i; |
| 56 | u32 tmp, div_val; |
| 57 | void *pll_base; |
| 58 | struct imx_int_pll_rate_table *rate; |
| 59 | |
| 60 | for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) { |
| 61 | if (freq == imx8mm_fracpll_tbl[i].rate) |
| 62 | break; |
| 63 | } |
| 64 | |
| 65 | if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) { |
| 66 | printf("No matched freq table %u\n", freq); |
| 67 | return -EINVAL; |
| 68 | } |
| 69 | |
| 70 | rate = &imx8mm_fracpll_tbl[i]; |
| 71 | |
| 72 | switch (pll) { |
| 73 | case ANATOP_DRAM_PLL: |
| 74 | setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); |
| 75 | setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); |
| 76 | writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); |
| 77 | |
| 78 | pll_base = &ana_pll->dram_pll_gnrl_ctl; |
| 79 | break; |
| 80 | case ANATOP_VIDEO_PLL: |
| 81 | pll_base = &ana_pll->video_pll1_gnrl_ctl; |
| 82 | break; |
| 83 | default: |
| 84 | return 0; |
| 85 | } |
| 86 | /* Bypass clock and set lock to pll output lock */ |
| 87 | tmp = readl(pll_base); |
| 88 | tmp |= BYPASS_MASK; |
| 89 | writel(tmp, pll_base); |
| 90 | |
| 91 | /* Enable RST */ |
| 92 | tmp &= ~RST_MASK; |
| 93 | writel(tmp, pll_base); |
| 94 | |
| 95 | div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | |
| 96 | (rate->sdiv << SDIV_SHIFT); |
| 97 | writel(div_val, pll_base + 4); |
| 98 | writel(rate->kdiv << KDIV_SHIFT, pll_base + 8); |
| 99 | |
| 100 | __udelay(100); |
| 101 | |
| 102 | /* Disable RST */ |
| 103 | tmp |= RST_MASK; |
| 104 | writel(tmp, pll_base); |
| 105 | |
| 106 | /* Wait Lock*/ |
| 107 | while (!(readl(pll_base) & LOCK_STATUS)) |
| 108 | ; |
| 109 | |
| 110 | /* Bypass */ |
| 111 | tmp &= ~BYPASS_MASK; |
| 112 | writel(tmp, pll_base); |
| 113 | |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | void dram_pll_init(ulong pll_val) |
| 118 | { |
| 119 | fracpll_configure(ANATOP_DRAM_PLL, pll_val); |
| 120 | } |
| 121 | |
| 122 | static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = { |
| 123 | DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2, |
| 124 | CLK_ROOT_PRE_DIV2), |
| 125 | DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2, |
| 126 | CLK_ROOT_PRE_DIV2), |
| 127 | DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3, |
| 128 | CLK_ROOT_PRE_DIV2), |
| 129 | }; |
| 130 | |
| 131 | void dram_enable_bypass(ulong clk_val) |
| 132 | { |
| 133 | int i; |
| 134 | struct dram_bypass_clk_setting *config; |
| 135 | |
| 136 | for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) { |
| 137 | if (clk_val == imx8mm_dram_bypass_tbl[i].clk) |
| 138 | break; |
| 139 | } |
| 140 | |
| 141 | if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) { |
| 142 | printf("No matched freq table %lu\n", clk_val); |
| 143 | return; |
| 144 | } |
| 145 | |
| 146 | config = &imx8mm_dram_bypass_tbl[i]; |
| 147 | |
| 148 | clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | |
| 149 | CLK_ROOT_SOURCE_SEL(config->alt_root_sel) | |
| 150 | CLK_ROOT_PRE_DIV(config->alt_pre_div)); |
| 151 | clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | |
| 152 | CLK_ROOT_SOURCE_SEL(config->apb_root_sel) | |
| 153 | CLK_ROOT_PRE_DIV(config->apb_pre_div)); |
| 154 | clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | |
| 155 | CLK_ROOT_SOURCE_SEL(1)); |
| 156 | } |
| 157 | |
| 158 | void dram_disable_bypass(void) |
| 159 | { |
| 160 | clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | |
| 161 | CLK_ROOT_SOURCE_SEL(0)); |
| 162 | clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | |
| 163 | CLK_ROOT_SOURCE_SEL(4) | |
| 164 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); |
| 165 | } |
| 166 | #endif |
| 167 | |
Peng Fan | 4e36e33 | 2020-07-09 11:06:24 +0800 | [diff] [blame] | 168 | int intpll_configure(enum pll_clocks pll, ulong freq) |
| 169 | { |
| 170 | void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl; |
| 171 | u32 pll_div_ctl_val, pll_clke_masks; |
| 172 | |
| 173 | switch (pll) { |
| 174 | case ANATOP_SYSTEM_PLL1: |
| 175 | pll_gnrl_ctl = &ana_pll->sys_pll1_gnrl_ctl; |
| 176 | pll_div_ctl = &ana_pll->sys_pll1_div_ctl; |
| 177 | pll_clke_masks = INTPLL_DIV20_CLKE_MASK | |
| 178 | INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK | |
| 179 | INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK | |
| 180 | INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK | |
| 181 | INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK; |
| 182 | break; |
| 183 | case ANATOP_SYSTEM_PLL2: |
| 184 | pll_gnrl_ctl = &ana_pll->sys_pll2_gnrl_ctl; |
| 185 | pll_div_ctl = &ana_pll->sys_pll2_div_ctl; |
| 186 | pll_clke_masks = INTPLL_DIV20_CLKE_MASK | |
| 187 | INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK | |
| 188 | INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK | |
| 189 | INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK | |
| 190 | INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK; |
| 191 | break; |
| 192 | case ANATOP_SYSTEM_PLL3: |
| 193 | pll_gnrl_ctl = &ana_pll->sys_pll3_gnrl_ctl; |
| 194 | pll_div_ctl = &ana_pll->sys_pll3_div_ctl; |
| 195 | pll_clke_masks = INTPLL_CLKE_MASK; |
| 196 | break; |
| 197 | case ANATOP_ARM_PLL: |
| 198 | pll_gnrl_ctl = &ana_pll->arm_pll_gnrl_ctl; |
| 199 | pll_div_ctl = &ana_pll->arm_pll_div_ctl; |
| 200 | pll_clke_masks = INTPLL_CLKE_MASK; |
| 201 | break; |
| 202 | case ANATOP_GPU_PLL: |
| 203 | pll_gnrl_ctl = &ana_pll->gpu_pll_gnrl_ctl; |
| 204 | pll_div_ctl = &ana_pll->gpu_pll_div_ctl; |
| 205 | pll_clke_masks = INTPLL_CLKE_MASK; |
| 206 | break; |
| 207 | case ANATOP_VPU_PLL: |
| 208 | pll_gnrl_ctl = &ana_pll->vpu_pll_gnrl_ctl; |
| 209 | pll_div_ctl = &ana_pll->vpu_pll_div_ctl; |
| 210 | pll_clke_masks = INTPLL_CLKE_MASK; |
| 211 | break; |
| 212 | default: |
| 213 | return -EINVAL; |
| 214 | }; |
| 215 | |
| 216 | switch (freq) { |
| 217 | case MHZ(600): |
| 218 | /* 24 * 0x12c / 3 / 2 ^ 2 */ |
| 219 | pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) | |
| 220 | INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2); |
| 221 | break; |
| 222 | case MHZ(750): |
| 223 | /* 24 * 0xfa / 2 / 2 ^ 2 */ |
| 224 | pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) | |
| 225 | INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2); |
| 226 | break; |
| 227 | case MHZ(800): |
| 228 | /* 24 * 0x190 / 3 / 2 ^ 2 */ |
| 229 | pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) | |
| 230 | INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2); |
| 231 | break; |
| 232 | case MHZ(1000): |
| 233 | /* 24 * 0xfa / 3 / 2 ^ 1 */ |
| 234 | pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) | |
| 235 | INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1); |
| 236 | break; |
| 237 | case MHZ(1200): |
| 238 | /* 24 * 0xc8 / 2 / 2 ^ 1 */ |
| 239 | pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) | |
| 240 | INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1); |
| 241 | break; |
| 242 | case MHZ(2000): |
| 243 | /* 24 * 0xfa / 3 / 2 ^ 0 */ |
| 244 | pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) | |
| 245 | INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0); |
| 246 | break; |
| 247 | default: |
| 248 | return -EINVAL; |
| 249 | }; |
| 250 | /* Bypass clock and set lock to pll output lock */ |
| 251 | setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK); |
| 252 | /* Enable reset */ |
| 253 | clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK); |
| 254 | /* Configure */ |
| 255 | writel(pll_div_ctl_val, pll_div_ctl); |
| 256 | |
| 257 | __udelay(100); |
| 258 | |
| 259 | /* Disable reset */ |
| 260 | setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK); |
| 261 | /* Wait Lock */ |
| 262 | while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK)) |
| 263 | ; |
| 264 | /* Clear bypass */ |
| 265 | clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK); |
| 266 | setbits_le32(pll_gnrl_ctl, pll_clke_masks); |
| 267 | |
| 268 | return 0; |
| 269 | } |
| 270 | |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 271 | void init_uart_clk(u32 index) |
| 272 | { |
| 273 | /* |
| 274 | * set uart clock root |
| 275 | * 24M OSC |
| 276 | */ |
| 277 | switch (index) { |
| 278 | case 0: |
| 279 | clock_enable(CCGR_UART1, 0); |
| 280 | clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | |
| 281 | CLK_ROOT_SOURCE_SEL(0)); |
| 282 | clock_enable(CCGR_UART1, 1); |
| 283 | return; |
| 284 | case 1: |
| 285 | clock_enable(CCGR_UART2, 0); |
| 286 | clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | |
| 287 | CLK_ROOT_SOURCE_SEL(0)); |
| 288 | clock_enable(CCGR_UART2, 1); |
| 289 | return; |
| 290 | case 2: |
| 291 | clock_enable(CCGR_UART3, 0); |
| 292 | clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | |
| 293 | CLK_ROOT_SOURCE_SEL(0)); |
| 294 | clock_enable(CCGR_UART3, 1); |
| 295 | return; |
| 296 | case 3: |
| 297 | clock_enable(CCGR_UART4, 0); |
| 298 | clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON | |
| 299 | CLK_ROOT_SOURCE_SEL(0)); |
| 300 | clock_enable(CCGR_UART4, 1); |
| 301 | return; |
| 302 | default: |
| 303 | printf("Invalid uart index\n"); |
| 304 | return; |
| 305 | } |
| 306 | } |
| 307 | |
| 308 | void init_wdog_clk(void) |
| 309 | { |
| 310 | clock_enable(CCGR_WDOG1, 0); |
| 311 | clock_enable(CCGR_WDOG2, 0); |
| 312 | clock_enable(CCGR_WDOG3, 0); |
| 313 | clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | |
| 314 | CLK_ROOT_SOURCE_SEL(0)); |
| 315 | clock_enable(CCGR_WDOG1, 1); |
| 316 | clock_enable(CCGR_WDOG2, 1); |
| 317 | clock_enable(CCGR_WDOG3, 1); |
| 318 | } |
| 319 | |
Peng Fan | c61ec9b | 2020-07-09 11:35:15 +0800 | [diff] [blame] | 320 | void init_clk_usdhc(u32 index) |
| 321 | { |
| 322 | /* |
| 323 | * set usdhc clock root |
| 324 | * sys pll1 400M |
| 325 | */ |
| 326 | switch (index) { |
| 327 | case 0: |
| 328 | clock_enable(CCGR_USDHC1, 0); |
| 329 | clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | |
| 330 | CLK_ROOT_SOURCE_SEL(1)); |
| 331 | clock_enable(CCGR_USDHC1, 1); |
| 332 | return; |
| 333 | case 1: |
| 334 | clock_enable(CCGR_USDHC2, 0); |
| 335 | clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | |
| 336 | CLK_ROOT_SOURCE_SEL(1)); |
| 337 | clock_enable(CCGR_USDHC2, 1); |
| 338 | return; |
| 339 | case 2: |
| 340 | clock_enable(CCGR_USDHC3, 0); |
| 341 | clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON | |
| 342 | CLK_ROOT_SOURCE_SEL(1)); |
| 343 | clock_enable(CCGR_USDHC3, 1); |
| 344 | return; |
| 345 | default: |
| 346 | printf("Invalid usdhc index\n"); |
| 347 | return; |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | void init_clk_ecspi(u32 index) |
| 352 | { |
| 353 | switch (index) { |
| 354 | case 0: |
| 355 | clock_enable(CCGR_ECSPI1, 0); |
| 356 | clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); |
| 357 | clock_enable(CCGR_ECSPI1, 1); |
| 358 | return; |
| 359 | case 1: |
| 360 | clock_enable(CCGR_ECSPI2, 0); |
| 361 | clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); |
| 362 | clock_enable(CCGR_ECSPI2, 1); |
| 363 | case 2: |
| 364 | clock_enable(CCGR_ECSPI3, 0); |
| 365 | clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); |
| 366 | clock_enable(CCGR_ECSPI3, 1); |
| 367 | return; |
| 368 | default: |
| 369 | printf("Invalid ecspi index\n"); |
| 370 | return; |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | void init_nand_clk(void) |
| 375 | { |
| 376 | /* |
| 377 | * set rawnand root |
| 378 | * sys pll1 400M |
| 379 | */ |
| 380 | clock_enable(CCGR_RAWNAND, 0); |
| 381 | clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON | |
| 382 | CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */ |
| 383 | clock_enable(CCGR_RAWNAND, 1); |
| 384 | } |
| 385 | |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 386 | int clock_init(void) |
| 387 | { |
| 388 | u32 val_cfg0; |
| 389 | |
| 390 | /* |
| 391 | * The gate is not exported to clk tree, so configure them here. |
| 392 | * According to ANAMIX SPEC |
| 393 | * sys pll1 fixed at 800MHz |
| 394 | * sys pll2 fixed at 1GHz |
| 395 | * Here we only enable the outputs. |
| 396 | */ |
| 397 | val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl); |
| 398 | val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | |
| 399 | INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK | |
| 400 | INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK | |
| 401 | INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK | |
| 402 | INTPLL_DIV20_CLKE_MASK; |
| 403 | writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl); |
| 404 | |
| 405 | val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl); |
| 406 | val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK | |
| 407 | INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK | |
| 408 | INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK | |
| 409 | INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK | |
| 410 | INTPLL_DIV20_CLKE_MASK; |
| 411 | writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl); |
| 412 | |
Peng Fan | 4e36e33 | 2020-07-09 11:06:24 +0800 | [diff] [blame] | 413 | /* Configure ARM at 1.2GHz */ |
| 414 | clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | |
| 415 | CLK_ROOT_SOURCE_SEL(2)); |
| 416 | |
| 417 | intpll_configure(ANATOP_ARM_PLL, MHZ(1200)); |
| 418 | |
| 419 | /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */ |
| 420 | clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1)); |
| 421 | |
Peng Fan | e565393 | 2020-07-09 11:18:50 +0800 | [diff] [blame] | 422 | if (is_imx8mn() || is_imx8mp()) |
| 423 | intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(600)); |
| 424 | else |
| 425 | intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750)); |
| 426 | |
| 427 | #ifdef CONFIG_IMX8MP |
| 428 | /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */ |
| 429 | /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */ |
| 430 | clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2)); |
| 431 | #else |
| 432 | clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2)); |
| 433 | |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 434 | /* config GIC to sys_pll2_100m */ |
| 435 | clock_enable(CCGR_GIC, 0); |
| 436 | clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | |
| 437 | CLK_ROOT_SOURCE_SEL(3)); |
| 438 | clock_enable(CCGR_GIC, 1); |
Peng Fan | e565393 | 2020-07-09 11:18:50 +0800 | [diff] [blame] | 439 | #endif |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 440 | |
| 441 | clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | |
| 442 | CLK_ROOT_SOURCE_SEL(1)); |
| 443 | |
| 444 | clock_enable(CCGR_DDR1, 0); |
| 445 | clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | |
| 446 | CLK_ROOT_SOURCE_SEL(1)); |
| 447 | clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | |
| 448 | CLK_ROOT_SOURCE_SEL(1)); |
| 449 | clock_enable(CCGR_DDR1, 1); |
| 450 | |
| 451 | init_wdog_clk(); |
| 452 | |
| 453 | clock_enable(CCGR_TEMP_SENSOR, 1); |
| 454 | |
| 455 | clock_enable(CCGR_SEC_DEBUG, 1); |
| 456 | |
| 457 | return 0; |
| 458 | }; |
| 459 | |
| 460 | u32 imx_get_uartclk(void) |
| 461 | { |
| 462 | return 24000000U; |
| 463 | } |
| 464 | |
Alifer Moraes | 3993110 | 2020-01-14 15:54:59 -0300 | [diff] [blame] | 465 | static u32 decode_intpll(enum clk_root_src intpll) |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 466 | { |
| 467 | u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask; |
| 468 | u32 main_div, pre_div, post_div, div; |
| 469 | u64 freq; |
| 470 | |
| 471 | switch (intpll) { |
| 472 | case ARM_PLL_CLK: |
| 473 | pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl); |
| 474 | pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl); |
| 475 | break; |
| 476 | case GPU_PLL_CLK: |
| 477 | pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl); |
| 478 | pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl); |
| 479 | break; |
| 480 | case VPU_PLL_CLK: |
| 481 | pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl); |
| 482 | pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl); |
| 483 | break; |
| 484 | case SYSTEM_PLL1_800M_CLK: |
| 485 | case SYSTEM_PLL1_400M_CLK: |
| 486 | case SYSTEM_PLL1_266M_CLK: |
| 487 | case SYSTEM_PLL1_200M_CLK: |
| 488 | case SYSTEM_PLL1_160M_CLK: |
| 489 | case SYSTEM_PLL1_133M_CLK: |
| 490 | case SYSTEM_PLL1_100M_CLK: |
| 491 | case SYSTEM_PLL1_80M_CLK: |
| 492 | case SYSTEM_PLL1_40M_CLK: |
| 493 | pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl); |
| 494 | pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl); |
| 495 | break; |
| 496 | case SYSTEM_PLL2_1000M_CLK: |
| 497 | case SYSTEM_PLL2_500M_CLK: |
| 498 | case SYSTEM_PLL2_333M_CLK: |
| 499 | case SYSTEM_PLL2_250M_CLK: |
| 500 | case SYSTEM_PLL2_200M_CLK: |
| 501 | case SYSTEM_PLL2_166M_CLK: |
| 502 | case SYSTEM_PLL2_125M_CLK: |
| 503 | case SYSTEM_PLL2_100M_CLK: |
| 504 | case SYSTEM_PLL2_50M_CLK: |
| 505 | pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl); |
| 506 | pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl); |
| 507 | break; |
| 508 | case SYSTEM_PLL3_CLK: |
| 509 | pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl); |
| 510 | pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl); |
| 511 | break; |
| 512 | default: |
| 513 | return -EINVAL; |
| 514 | } |
| 515 | |
| 516 | /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */ |
| 517 | if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0) |
| 518 | return 0; |
| 519 | |
| 520 | if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0) |
| 521 | return 0; |
| 522 | |
| 523 | /* |
| 524 | * When BYPASS is equal to 1, PLL enters the bypass mode |
| 525 | * regardless of the values of RESETB |
| 526 | */ |
| 527 | if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) |
| 528 | return 24000000u; |
| 529 | |
| 530 | if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { |
| 531 | puts("pll not locked\n"); |
| 532 | return 0; |
| 533 | } |
| 534 | |
| 535 | switch (intpll) { |
| 536 | case ARM_PLL_CLK: |
| 537 | case GPU_PLL_CLK: |
| 538 | case VPU_PLL_CLK: |
| 539 | case SYSTEM_PLL3_CLK: |
| 540 | case SYSTEM_PLL1_800M_CLK: |
| 541 | case SYSTEM_PLL2_1000M_CLK: |
| 542 | pll_clke_mask = INTPLL_CLKE_MASK; |
| 543 | div = 1; |
| 544 | break; |
| 545 | |
| 546 | case SYSTEM_PLL1_400M_CLK: |
| 547 | case SYSTEM_PLL2_500M_CLK: |
| 548 | pll_clke_mask = INTPLL_DIV2_CLKE_MASK; |
| 549 | div = 2; |
| 550 | break; |
| 551 | |
| 552 | case SYSTEM_PLL1_266M_CLK: |
| 553 | case SYSTEM_PLL2_333M_CLK: |
| 554 | pll_clke_mask = INTPLL_DIV3_CLKE_MASK; |
| 555 | div = 3; |
| 556 | break; |
| 557 | |
| 558 | case SYSTEM_PLL1_200M_CLK: |
| 559 | case SYSTEM_PLL2_250M_CLK: |
| 560 | pll_clke_mask = INTPLL_DIV4_CLKE_MASK; |
| 561 | div = 4; |
| 562 | break; |
| 563 | |
| 564 | case SYSTEM_PLL1_160M_CLK: |
| 565 | case SYSTEM_PLL2_200M_CLK: |
| 566 | pll_clke_mask = INTPLL_DIV5_CLKE_MASK; |
| 567 | div = 5; |
| 568 | break; |
| 569 | |
| 570 | case SYSTEM_PLL1_133M_CLK: |
| 571 | case SYSTEM_PLL2_166M_CLK: |
| 572 | pll_clke_mask = INTPLL_DIV6_CLKE_MASK; |
| 573 | div = 6; |
| 574 | break; |
| 575 | |
| 576 | case SYSTEM_PLL1_100M_CLK: |
| 577 | case SYSTEM_PLL2_125M_CLK: |
| 578 | pll_clke_mask = INTPLL_DIV8_CLKE_MASK; |
| 579 | div = 8; |
| 580 | break; |
| 581 | |
| 582 | case SYSTEM_PLL1_80M_CLK: |
| 583 | case SYSTEM_PLL2_100M_CLK: |
| 584 | pll_clke_mask = INTPLL_DIV10_CLKE_MASK; |
| 585 | div = 10; |
| 586 | break; |
| 587 | |
| 588 | case SYSTEM_PLL1_40M_CLK: |
| 589 | case SYSTEM_PLL2_50M_CLK: |
| 590 | pll_clke_mask = INTPLL_DIV20_CLKE_MASK; |
| 591 | div = 20; |
| 592 | break; |
| 593 | default: |
| 594 | return -EINVAL; |
| 595 | } |
| 596 | |
| 597 | if ((pll_gnrl_ctl & pll_clke_mask) == 0) |
| 598 | return 0; |
| 599 | |
| 600 | main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >> |
| 601 | INTPLL_MAIN_DIV_SHIFT; |
| 602 | pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >> |
| 603 | INTPLL_PRE_DIV_SHIFT; |
| 604 | post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >> |
| 605 | INTPLL_POST_DIV_SHIFT; |
| 606 | |
| 607 | /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */ |
| 608 | freq = 24000000ULL * main_div; |
| 609 | return lldiv(freq, pre_div * (1 << post_div) * div); |
| 610 | } |
| 611 | |
Alifer Moraes | 3993110 | 2020-01-14 15:54:59 -0300 | [diff] [blame] | 612 | static u32 decode_fracpll(enum clk_root_src frac_pll) |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 613 | { |
| 614 | u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1; |
| 615 | u32 main_div, pre_div, post_div, k; |
| 616 | |
| 617 | switch (frac_pll) { |
| 618 | case DRAM_PLL1_CLK: |
| 619 | pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl); |
| 620 | pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0); |
| 621 | pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1); |
| 622 | break; |
| 623 | case AUDIO_PLL1_CLK: |
| 624 | pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl); |
| 625 | pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0); |
| 626 | pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1); |
| 627 | break; |
| 628 | case AUDIO_PLL2_CLK: |
| 629 | pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl); |
| 630 | pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0); |
| 631 | pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1); |
| 632 | break; |
| 633 | case VIDEO_PLL_CLK: |
| 634 | pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl); |
| 635 | pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0); |
| 636 | pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1); |
| 637 | break; |
| 638 | default: |
| 639 | printf("Not supported\n"); |
| 640 | return 0; |
| 641 | } |
| 642 | |
| 643 | /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */ |
Ye Li | cc643ea | 2020-03-23 19:54:29 -0700 | [diff] [blame] | 644 | if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 645 | return 0; |
| 646 | |
Ye Li | cc643ea | 2020-03-23 19:54:29 -0700 | [diff] [blame] | 647 | if ((pll_gnrl_ctl & RST_MASK) == 0) |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 648 | return 0; |
| 649 | /* |
| 650 | * When BYPASS is equal to 1, PLL enters the bypass mode |
| 651 | * regardless of the values of RESETB |
| 652 | */ |
Ye Li | cc643ea | 2020-03-23 19:54:29 -0700 | [diff] [blame] | 653 | if (pll_gnrl_ctl & BYPASS_MASK) |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 654 | return 24000000u; |
| 655 | |
Ye Li | cc643ea | 2020-03-23 19:54:29 -0700 | [diff] [blame] | 656 | if (!(pll_gnrl_ctl & LOCK_STATUS)) { |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 657 | puts("pll not locked\n"); |
| 658 | return 0; |
| 659 | } |
| 660 | |
Ye Li | cc643ea | 2020-03-23 19:54:29 -0700 | [diff] [blame] | 661 | if (!(pll_gnrl_ctl & CLKE_MASK)) |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 662 | return 0; |
| 663 | |
Ye Li | cc643ea | 2020-03-23 19:54:29 -0700 | [diff] [blame] | 664 | main_div = (pll_fdiv_ctl0 & MDIV_MASK) >> |
| 665 | MDIV_SHIFT; |
| 666 | pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >> |
| 667 | PDIV_SHIFT; |
| 668 | post_div = (pll_fdiv_ctl0 & SDIV_MASK) >> |
| 669 | SDIV_SHIFT; |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 670 | |
Ye Li | cc643ea | 2020-03-23 19:54:29 -0700 | [diff] [blame] | 671 | k = pll_fdiv_ctl1 & KDIV_MASK; |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 672 | |
| 673 | return lldiv((main_div * 65536 + k) * 24000000ULL, |
| 674 | 65536 * pre_div * (1 << post_div)); |
| 675 | } |
| 676 | |
Alifer Moraes | 3993110 | 2020-01-14 15:54:59 -0300 | [diff] [blame] | 677 | static u32 get_root_src_clk(enum clk_root_src root_src) |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 678 | { |
| 679 | switch (root_src) { |
| 680 | case OSC_24M_CLK: |
| 681 | return 24000000u; |
| 682 | case OSC_HDMI_CLK: |
| 683 | return 26000000u; |
| 684 | case OSC_32K_CLK: |
| 685 | return 32000u; |
| 686 | case ARM_PLL_CLK: |
| 687 | case GPU_PLL_CLK: |
| 688 | case VPU_PLL_CLK: |
| 689 | case SYSTEM_PLL1_800M_CLK: |
| 690 | case SYSTEM_PLL1_400M_CLK: |
| 691 | case SYSTEM_PLL1_266M_CLK: |
| 692 | case SYSTEM_PLL1_200M_CLK: |
| 693 | case SYSTEM_PLL1_160M_CLK: |
| 694 | case SYSTEM_PLL1_133M_CLK: |
| 695 | case SYSTEM_PLL1_100M_CLK: |
| 696 | case SYSTEM_PLL1_80M_CLK: |
| 697 | case SYSTEM_PLL1_40M_CLK: |
| 698 | case SYSTEM_PLL2_1000M_CLK: |
| 699 | case SYSTEM_PLL2_500M_CLK: |
| 700 | case SYSTEM_PLL2_333M_CLK: |
| 701 | case SYSTEM_PLL2_250M_CLK: |
| 702 | case SYSTEM_PLL2_200M_CLK: |
| 703 | case SYSTEM_PLL2_166M_CLK: |
| 704 | case SYSTEM_PLL2_125M_CLK: |
| 705 | case SYSTEM_PLL2_100M_CLK: |
| 706 | case SYSTEM_PLL2_50M_CLK: |
| 707 | case SYSTEM_PLL3_CLK: |
| 708 | return decode_intpll(root_src); |
| 709 | case DRAM_PLL1_CLK: |
| 710 | case AUDIO_PLL1_CLK: |
| 711 | case AUDIO_PLL2_CLK: |
| 712 | case VIDEO_PLL_CLK: |
| 713 | return decode_fracpll(root_src); |
Peng Fan | 4e36e33 | 2020-07-09 11:06:24 +0800 | [diff] [blame] | 714 | case ARM_A53_ALT_CLK: |
| 715 | return get_root_clk(ARM_A53_CLK_ROOT); |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 716 | default: |
| 717 | return 0; |
| 718 | } |
| 719 | |
| 720 | return 0; |
| 721 | } |
| 722 | |
Alifer Moraes | 3993110 | 2020-01-14 15:54:59 -0300 | [diff] [blame] | 723 | static u32 get_root_clk(enum clk_root_index clock_id) |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 724 | { |
| 725 | enum clk_root_src root_src; |
| 726 | u32 post_podf, pre_podf, root_src_clk; |
| 727 | |
| 728 | if (clock_root_enabled(clock_id) <= 0) |
| 729 | return 0; |
| 730 | |
| 731 | if (clock_get_prediv(clock_id, &pre_podf) < 0) |
| 732 | return 0; |
| 733 | |
| 734 | if (clock_get_postdiv(clock_id, &post_podf) < 0) |
| 735 | return 0; |
| 736 | |
| 737 | if (clock_get_src(clock_id, &root_src) < 0) |
| 738 | return 0; |
| 739 | |
| 740 | root_src_clk = get_root_src_clk(root_src); |
| 741 | |
| 742 | return root_src_clk / (post_podf + 1) / (pre_podf + 1); |
| 743 | } |
| 744 | |
Peng Fan | 4e36e33 | 2020-07-09 11:06:24 +0800 | [diff] [blame] | 745 | u32 get_arm_core_clk(void) |
| 746 | { |
| 747 | enum clk_root_src root_src; |
| 748 | u32 root_src_clk; |
| 749 | |
| 750 | if (clock_get_src(CORE_SEL_CFG, &root_src) < 0) |
| 751 | return 0; |
| 752 | |
| 753 | root_src_clk = get_root_src_clk(root_src); |
| 754 | |
| 755 | return root_src_clk; |
| 756 | } |
| 757 | |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 758 | u32 mxc_get_clock(enum mxc_clock clk) |
| 759 | { |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 760 | u32 val; |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 761 | |
| 762 | switch (clk) { |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 763 | case MXC_ARM_CLK: |
Peng Fan | 4e36e33 | 2020-07-09 11:06:24 +0800 | [diff] [blame] | 764 | return get_arm_core_clk(); |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 765 | case MXC_IPG_CLK: |
| 766 | clock_get_target_val(IPG_CLK_ROOT, &val); |
| 767 | val = val & 0x3; |
| 768 | return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1); |
| 769 | case MXC_CSPI_CLK: |
| 770 | return get_root_clk(ECSPI1_CLK_ROOT); |
| 771 | case MXC_ESDHC_CLK: |
| 772 | return get_root_clk(USDHC1_CLK_ROOT); |
| 773 | case MXC_ESDHC2_CLK: |
| 774 | return get_root_clk(USDHC2_CLK_ROOT); |
| 775 | case MXC_ESDHC3_CLK: |
| 776 | return get_root_clk(USDHC3_CLK_ROOT); |
| 777 | case MXC_I2C_CLK: |
| 778 | return get_root_clk(I2C1_CLK_ROOT); |
| 779 | case MXC_UART_CLK: |
| 780 | return get_root_clk(UART1_CLK_ROOT); |
| 781 | case MXC_QSPI_CLK: |
| 782 | return get_root_clk(QSPI_CLK_ROOT); |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 783 | default: |
Peng Fan | 60c29bb | 2019-12-30 16:52:30 +0800 | [diff] [blame] | 784 | printf("Unsupported mxc_clock %d\n", clk); |
| 785 | break; |
Peng Fan | 9987846 | 2019-08-27 06:25:51 +0000 | [diff] [blame] | 786 | } |
| 787 | |
| 788 | return 0; |
| 789 | } |
Marek Vasut | 363725d | 2020-04-24 21:37:26 +0200 | [diff] [blame] | 790 | |
Peng Fan | 1dd259c | 2020-07-09 13:14:20 +0800 | [diff] [blame^] | 791 | #ifdef CONFIG_DWC_ETH_QOS |
| 792 | int set_clk_eqos(enum enet_freq type) |
| 793 | { |
| 794 | u32 target; |
| 795 | u32 enet1_ref; |
| 796 | |
| 797 | switch (type) { |
| 798 | case ENET_125MHZ: |
| 799 | enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; |
| 800 | break; |
| 801 | case ENET_50MHZ: |
| 802 | enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; |
| 803 | break; |
| 804 | case ENET_25MHZ: |
| 805 | enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; |
| 806 | break; |
| 807 | default: |
| 808 | return -EINVAL; |
| 809 | } |
| 810 | |
| 811 | /* disable the clock first */ |
| 812 | clock_enable(CCGR_QOS_ETHENET, 0); |
| 813 | clock_enable(CCGR_SDMA2, 0); |
| 814 | |
| 815 | /* set enet axi clock 266Mhz */ |
| 816 | target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | |
| 817 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | |
| 818 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); |
| 819 | clock_set_target_val(ENET_AXI_CLK_ROOT, target); |
| 820 | |
| 821 | target = CLK_ROOT_ON | enet1_ref | |
| 822 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | |
| 823 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); |
| 824 | clock_set_target_val(ENET_QOS_CLK_ROOT, target); |
| 825 | |
| 826 | target = CLK_ROOT_ON | |
| 827 | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | |
| 828 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | |
| 829 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); |
| 830 | clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target); |
| 831 | |
| 832 | /* enable clock */ |
| 833 | clock_enable(CCGR_QOS_ETHENET, 1); |
| 834 | clock_enable(CCGR_SDMA2, 1); |
| 835 | |
| 836 | return 0; |
| 837 | } |
| 838 | |
| 839 | int imx_eqos_txclk_set_rate(u32 rate) |
| 840 | { |
| 841 | u32 val; |
| 842 | u32 eqos_post_div; |
| 843 | |
| 844 | /* disable the clock first */ |
| 845 | clock_enable(CCGR_QOS_ETHENET, 0); |
| 846 | clock_enable(CCGR_SDMA2, 0); |
| 847 | |
| 848 | switch (rate) { |
| 849 | case 125000000: |
| 850 | eqos_post_div = 1; |
| 851 | break; |
| 852 | case 25000000: |
| 853 | eqos_post_div = 125000000 / 25000000; |
| 854 | break; |
| 855 | case 2500000: |
| 856 | eqos_post_div = 125000000 / 2500000; |
| 857 | break; |
| 858 | default: |
| 859 | return -EINVAL; |
| 860 | } |
| 861 | |
| 862 | clock_get_target_val(ENET_QOS_CLK_ROOT, &val); |
| 863 | val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK); |
| 864 | val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | |
| 865 | CLK_ROOT_POST_DIV(eqos_post_div - 1); |
| 866 | clock_set_target_val(ENET_QOS_CLK_ROOT, val); |
| 867 | |
| 868 | /* enable clock */ |
| 869 | clock_enable(CCGR_QOS_ETHENET, 1); |
| 870 | clock_enable(CCGR_SDMA2, 1); |
| 871 | |
| 872 | return 0; |
| 873 | } |
| 874 | |
| 875 | u32 imx_get_eqos_csr_clk(void) |
| 876 | { |
| 877 | return get_root_clk(ENET_AXI_CLK_ROOT); |
| 878 | } |
| 879 | #endif |
| 880 | |
Marek Vasut | 363725d | 2020-04-24 21:37:26 +0200 | [diff] [blame] | 881 | #ifdef CONFIG_FEC_MXC |
| 882 | int set_clk_enet(enum enet_freq type) |
| 883 | { |
| 884 | u32 target; |
| 885 | u32 enet1_ref; |
| 886 | |
| 887 | switch (type) { |
| 888 | case ENET_125MHZ: |
| 889 | enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; |
| 890 | break; |
| 891 | case ENET_50MHZ: |
| 892 | enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; |
| 893 | break; |
| 894 | case ENET_25MHZ: |
| 895 | enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; |
| 896 | break; |
| 897 | default: |
| 898 | return -EINVAL; |
| 899 | } |
| 900 | |
| 901 | /* disable the clock first */ |
| 902 | clock_enable(CCGR_ENET1, 0); |
| 903 | clock_enable(CCGR_SIM_ENET, 0); |
| 904 | |
| 905 | /* set enet axi clock 266Mhz */ |
| 906 | target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | |
| 907 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | |
| 908 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); |
| 909 | clock_set_target_val(ENET_AXI_CLK_ROOT, target); |
| 910 | |
| 911 | target = CLK_ROOT_ON | enet1_ref | |
| 912 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | |
| 913 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); |
| 914 | clock_set_target_val(ENET_REF_CLK_ROOT, target); |
| 915 | |
| 916 | target = CLK_ROOT_ON | |
| 917 | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | |
| 918 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | |
| 919 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); |
| 920 | clock_set_target_val(ENET_TIMER_CLK_ROOT, target); |
| 921 | |
| 922 | /* enable clock */ |
| 923 | clock_enable(CCGR_SIM_ENET, 1); |
| 924 | clock_enable(CCGR_ENET1, 1); |
| 925 | |
| 926 | return 0; |
| 927 | } |
| 928 | #endif |