Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Tom Rini | 0634fc0 | 2014-06-05 11:15:29 -0400 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 |
| 4 | * Texas Instruments, <www.ti.com> |
Tom Rini | 0634fc0 | 2014-06-05 11:15:29 -0400 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __POWER_TPS65218_H__ |
| 8 | #define __POWER_TPS65218_H__ |
| 9 | |
Nikita Kiryanov | a5c71ff | 2016-02-19 19:19:46 +0200 | [diff] [blame] | 10 | #include <linux/bitops.h> |
| 11 | |
Tom Rini | 0634fc0 | 2014-06-05 11:15:29 -0400 | [diff] [blame] | 12 | /* I2C chip address */ |
| 13 | #define TPS65218_CHIP_PM 0x24 |
| 14 | |
| 15 | /* Registers */ |
| 16 | enum { |
| 17 | TPS65218_CHIPID = 0x00, |
| 18 | TPS65218_INT1, |
| 19 | TPS65218_INT2, |
| 20 | TPS65218_INT_MASK1, |
| 21 | TPS65218_INT_MASK2, |
| 22 | TPS65218_STATUS, |
| 23 | TPS65218_CONTROL, |
| 24 | TPS65218_FLAG, |
| 25 | TPS65218_PASSWORD = 0x10, |
| 26 | TPS65218_ENABLE1, |
| 27 | TPS65218_ENABLE2, |
| 28 | TPS65218_CONFIG1, |
| 29 | TPS65218_CONFIG2, |
| 30 | TPS65218_CONFIG3, |
| 31 | TPS65218_DCDC1, |
| 32 | TPS65218_DCDC2, |
| 33 | TPS65218_DCDC3, |
| 34 | TPS65218_DCDC4, |
| 35 | TPS65218_SLEW, |
| 36 | TPS65218_LDO1, |
| 37 | TPS65218_SEQ1 = 0x20, |
| 38 | TPS65218_SEQ2, |
| 39 | TPS65218_SEQ3, |
| 40 | TPS65218_SEQ4, |
| 41 | TPS65218_SEQ5, |
| 42 | TPS65218_SEQ6, |
| 43 | TPS65218_SEQ7, |
| 44 | TPS65218_PMIC_NUM_OF_REGS, |
| 45 | }; |
| 46 | |
| 47 | #define TPS65218_PROT_LEVEL_NONE 0x00 |
| 48 | #define TPS65218_PROT_LEVEL_1 0x01 |
| 49 | #define TPS65218_PROT_LEVEL_2 0x02 |
| 50 | |
| 51 | #define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00 |
| 52 | #define TPS65218_PASSWORD_UNLOCK 0x7D |
| 53 | |
| 54 | #define TPS65218_DCDC_GO 0x80 |
| 55 | |
| 56 | #define TPS65218_MASK_ALL_BITS 0xFF |
| 57 | |
Keerthy | 7cac656 | 2017-05-24 10:19:27 +0530 | [diff] [blame] | 58 | #define TPS65218_DCDC_VSEL_MASK 0x3F |
| 59 | |
Felipe Balbi | 8f2994b | 2014-12-22 16:26:14 -0600 | [diff] [blame] | 60 | #define TPS65218_DCDC_VOLT_SEL_0950MV 0x0a |
Tom Rini | 0634fc0 | 2014-06-05 11:15:29 -0400 | [diff] [blame] | 61 | #define TPS65218_DCDC_VOLT_SEL_1100MV 0x19 |
Felipe Balbi | 8f2994b | 2014-12-22 16:26:14 -0600 | [diff] [blame] | 62 | #define TPS65218_DCDC_VOLT_SEL_1200MV 0x23 |
| 63 | #define TPS65218_DCDC_VOLT_SEL_1260MV 0x29 |
Tom Rini | 0634fc0 | 2014-06-05 11:15:29 -0400 | [diff] [blame] | 64 | #define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 |
Keerthy | 6417a73 | 2017-06-02 15:00:31 +0530 | [diff] [blame] | 65 | #define TPS65218_DCDC3_VOLT_SEL_1350MV 0x12 |
Keerthy | 00344c4 | 2018-05-02 15:06:31 +0530 | [diff] [blame] | 66 | #define TPS65218_DCDC3_VOLT_SEL_1200MV 0xC |
Tom Rini | 0634fc0 | 2014-06-05 11:15:29 -0400 | [diff] [blame] | 67 | |
Nikita Kiryanov | a5c71ff | 2016-02-19 19:19:46 +0200 | [diff] [blame] | 68 | #define TPS65218_CC_STAT (BIT(0) | BIT(1)) |
| 69 | #define TPS65218_STATE (BIT(2) | BIT(3)) |
| 70 | #define TPS65218_PB_STATE BIT(4) |
| 71 | #define TPS65218_AC_STATE BIT(5) |
| 72 | #define TPS65218_EE BIT(6) |
| 73 | #define TPS65218_FSEAL BIT(7) |
| 74 | |
| 75 | int tps65218_reg_read(uchar dest_reg, uchar *dest_val); |
Tom Rini | 0634fc0 | 2014-06-05 11:15:29 -0400 | [diff] [blame] | 76 | int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, |
| 77 | uchar mask); |
| 78 | int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); |
Nikita Kiryanov | a5c71ff | 2016-02-19 19:19:46 +0200 | [diff] [blame] | 79 | int tps65218_toggle_fseal(void); |
| 80 | int tps65218_lock_fseal(void); |
Tom Rini | 60d2f6f | 2014-06-23 16:06:29 -0400 | [diff] [blame] | 81 | int power_tps65218_init(unsigned char bus); |
Tom Rini | 0634fc0 | 2014-06-05 11:15:29 -0400 | [diff] [blame] | 82 | #endif /* __POWER_TPS65218_H__ */ |