blob: 448bc5328673d1083e6717e3beed454502b46900 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek58f865f2015-04-15 13:36:40 +02002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
Michal Simeka8c94362023-07-10 14:35:49 +02004 * Michal Simek <michal.simek@amd.com>
Michal Simek58f865f2015-04-15 13:36:40 +02005 */
6
Tom Rinidec7ea02024-05-20 13:35:03 -06007#include <config.h>
Simon Glass970b61e2019-11-14 12:57:09 -07008#include <cpu_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060010#include <vsprintf.h>
Michal Simeka7acb532023-06-23 14:51:57 +020011#include <zynqmp_firmware.h>
Michal Simek58f865f2015-04-15 13:36:40 +020012#include <asm/arch/hardware.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/io.h>
Padmarao Begari384e25b2024-09-30 10:08:13 +053015#include <linux/bitfield.h>
Simon Glassdbd79542020-05-10 11:40:11 -060016#include <linux/delay.h>
Padmarao Begari384e25b2024-09-30 10:08:13 +053017#include <linux/errno.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060018#include <linux/string.h>
Michal Simek58f865f2015-04-15 13:36:40 +020019
20#define LOCK 0
21#define SPLIT 1
22
23#define HALT 0
24#define RELEASE 1
25
26#define ZYNQMP_BOOTADDR_HIGH_MASK 0xFFFFFFFF
27#define ZYNQMP_R5_HIVEC_ADDR 0xFFFF0000
28#define ZYNQMP_R5_LOVEC_ADDR 0x0
29#define ZYNQMP_RPU_CFG_CPU_HALT_MASK 0x01
30#define ZYNQMP_RPU_CFG_HIVEC_MASK 0x04
31#define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08
32#define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40
33#define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10
34
35#define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04
36#define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK 0x01
37#define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02
38#define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
39
Ashok Reddy Somab43d3cf2023-04-05 15:06:45 +020040#define ZYNQMP_R5_0_TCM_START_ADDR 0xFFE00000
41#define ZYNQMP_R5_1_TCM_START_ADDR 0xFFE90000
Michal Simek58f865f2015-04-15 13:36:40 +020042#define ZYNQMP_TCM_BOTH_SIZE 0x40000
43
44#define ZYNQMP_CORE_APU0 0
45#define ZYNQMP_CORE_APU3 3
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -060046#define ZYNQMP_CORE_RPU0 4
47#define ZYNQMP_CORE_RPU1 5
Michal Simek58f865f2015-04-15 13:36:40 +020048
49#define ZYNQMP_MAX_CORES 6
50
Lukas Funkec6f90582022-10-28 14:15:47 +020051#define ZYNQMP_RPU0_USE_MASK BIT(1)
52#define ZYNQMP_RPU1_USE_MASK BIT(2)
53
Michal Simek58f865f2015-04-15 13:36:40 +020054int is_core_valid(unsigned int core)
55{
56 if (core < ZYNQMP_MAX_CORES)
57 return 1;
58
59 return 0;
60}
61
Michal Simek1669e182018-06-13 08:56:31 +020062int cpu_reset(u32 nr)
Michal Simek58f865f2015-04-15 13:36:40 +020063{
64 puts("Feature is not implemented.\n");
65 return 0;
66}
67
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -060068static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
Michal Simek58f865f2015-04-15 13:36:40 +020069{
70 u32 tmp;
71
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -060072 if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
73 tmp = readl(&rpu_base->rpu0_cfg);
74 if (halt == HALT)
75 tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
76 else
77 tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
78 writel(tmp, &rpu_base->rpu0_cfg);
79 }
Michal Simek58f865f2015-04-15 13:36:40 +020080
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -060081 if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
Michal Simek58f865f2015-04-15 13:36:40 +020082 tmp = readl(&rpu_base->rpu1_cfg);
83 if (halt == HALT)
84 tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
85 else
86 tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
87 writel(tmp, &rpu_base->rpu1_cfg);
88 }
89}
90
91static void set_r5_tcm_mode(u8 mode)
92{
93 u32 tmp;
94
95 tmp = readl(&rpu_base->rpu_glbl_ctrl);
96 if (mode == LOCK) {
97 tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
98 tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
99 ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
100 } else {
101 tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
102 tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
103 ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK);
104 }
105
106 writel(tmp, &rpu_base->rpu_glbl_ctrl);
107}
108
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600109static void set_r5_reset(u32 nr, u8 mode)
Michal Simek58f865f2015-04-15 13:36:40 +0200110{
111 u32 tmp;
112
113 tmp = readl(&crlapb_base->rst_lpd_top);
Neal Fragerd929bbf2022-05-04 09:12:26 +0200114 if (mode == LOCK) {
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600115 tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
Neal Fragerd929bbf2022-05-04 09:12:26 +0200116 ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK |
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600117 ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
Neal Fragerd929bbf2022-05-04 09:12:26 +0200118 } else {
119 if (nr == ZYNQMP_CORE_RPU0) {
120 tmp |= ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK;
121 if (tmp & ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK)
122 tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK;
123 } else {
124 tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
125 if (tmp & ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK)
126 tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK;
127 }
128 }
Michal Simek58f865f2015-04-15 13:36:40 +0200129
130 writel(tmp, &crlapb_base->rst_lpd_top);
131}
132
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600133static void release_r5_reset(u32 nr, u8 mode)
Michal Simek58f865f2015-04-15 13:36:40 +0200134{
135 u32 tmp;
136
137 tmp = readl(&crlapb_base->rst_lpd_top);
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600138 if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
139 tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
140 ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
Michal Simek58f865f2015-04-15 13:36:40 +0200141
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600142 if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
143 tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
144 ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
Michal Simek58f865f2015-04-15 13:36:40 +0200145
146 writel(tmp, &crlapb_base->rst_lpd_top);
147}
148
149static void enable_clock_r5(void)
150{
151 u32 tmp;
152
153 tmp = readl(&crlapb_base->cpu_r5_ctrl);
154 tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
155 writel(tmp, &crlapb_base->cpu_r5_ctrl);
156
157 /* Give some delay for clock
Robert P. J. Day8d56db92016-07-15 13:44:45 -0400158 * to propagate */
Michal Simek58f865f2015-04-15 13:36:40 +0200159 udelay(0x500);
160}
161
Neal Fragerd929bbf2022-05-04 09:12:26 +0200162static int check_r5_mode(void)
163{
164 u32 tmp;
165
166 tmp = readl(&rpu_base->rpu_glbl_ctrl);
167 if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK)
168 return SPLIT;
169
170 return LOCK;
171}
172
Michal Simek1669e182018-06-13 08:56:31 +0200173int cpu_disable(u32 nr)
Michal Simek58f865f2015-04-15 13:36:40 +0200174{
Venkatesh Yadav Abbarapuae8bc3d2022-10-04 11:04:54 +0530175 if (nr <= ZYNQMP_CORE_APU3) {
Michal Simek58f865f2015-04-15 13:36:40 +0200176 u32 val = readl(&crfapb_base->rst_fpd_apu);
177 val |= 1 << nr;
178 writel(val, &crfapb_base->rst_fpd_apu);
179 } else {
Neal Fragerd929bbf2022-05-04 09:12:26 +0200180 set_r5_reset(nr, check_r5_mode());
Michal Simek58f865f2015-04-15 13:36:40 +0200181 }
182
183 return 0;
184}
185
Michal Simek1669e182018-06-13 08:56:31 +0200186int cpu_status(u32 nr)
Michal Simek58f865f2015-04-15 13:36:40 +0200187{
Venkatesh Yadav Abbarapuae8bc3d2022-10-04 11:04:54 +0530188 if (nr <= ZYNQMP_CORE_APU3) {
Michal Simek58f865f2015-04-15 13:36:40 +0200189 u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
190 u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) +
191 nr * 8);
192 u32 val = readl(&crfapb_base->rst_fpd_apu);
193 val &= 1 << nr;
194 printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n",
195 nr, val ? "OFF" : "ON" , addr_high, addr_low);
196 } else {
197 u32 val = readl(&crlapb_base->rst_lpd_top);
198 val &= 1 << (nr - 4);
199 printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON");
200 }
201
202 return 0;
203}
204
205static void set_r5_start(u8 high)
206{
207 u32 tmp;
208
209 tmp = readl(&rpu_base->rpu0_cfg);
210 if (high)
211 tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
212 else
213 tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
214 writel(tmp, &rpu_base->rpu0_cfg);
215
216 tmp = readl(&rpu_base->rpu1_cfg);
217 if (high)
218 tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
219 else
220 tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
221 writel(tmp, &rpu_base->rpu1_cfg);
222}
223
Ashok Reddy Somab43d3cf2023-04-05 15:06:45 +0200224static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr)
Michal Simekf5005ce2015-05-22 13:28:23 +0200225{
226 if (boot_addr) {
Ashok Reddy Somab43d3cf2023-04-05 15:06:45 +0200227 u64 tcm_start_addr = ZYNQMP_R5_0_TCM_START_ADDR;
228
229 if (nr == ZYNQMP_CORE_RPU1)
230 tcm_start_addr = ZYNQMP_R5_1_TCM_START_ADDR;
231
Michal Simekf5005ce2015-05-22 13:28:23 +0200232 /*
233 * Boot trampoline is simple ASM code below.
234 *
235 * b over;
236 * label:
237 * .word 0
238 * over: ldr r0, =label
239 * ldr r1, [r0]
240 * bx r1
241 */
242 debug("Write boot trampoline for %x\n", boot_addr);
Ashok Reddy Somab43d3cf2023-04-05 15:06:45 +0200243 writel(0xea000000, tcm_start_addr);
244 writel(boot_addr, tcm_start_addr + 0x4);
245 writel(0xe59f0004, tcm_start_addr + 0x8);
246 writel(0xe5901000, tcm_start_addr + 0xc);
247 writel(0xe12fff11, tcm_start_addr + 0x10);
248 writel(0x00000004, tcm_start_addr + 0x14);
Michal Simekf5005ce2015-05-22 13:28:23 +0200249 }
250}
251
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +0530252void initialize_tcm(bool mode)
253{
254 if (!mode) {
255 set_r5_tcm_mode(LOCK);
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600256 set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK);
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +0530257 enable_clock_r5();
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600258 release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +0530259 } else {
260 set_r5_tcm_mode(SPLIT);
Neal Frager7aba2552023-03-23 08:25:06 +0000261 set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT);
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600262 set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +0530263 enable_clock_r5();
Neal Frager7aba2552023-03-23 08:25:06 +0000264 release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT);
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600265 release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +0530266 }
Lukas Funkec6f90582022-10-28 14:15:47 +0200267}
268
Padmarao Begari384e25b2024-09-30 10:08:13 +0530269int check_tcm_mode(bool mode)
270{
271 u32 tmp, cpu_state;
272 bool mode_prev;
273
274 tmp = readl(&rpu_base->rpu_glbl_ctrl);
275 mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp);
276
277 tmp = readl(&crlapb_base->rst_lpd_top);
278 cpu_state = FIELD_GET(ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK |
279 ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp);
280 cpu_state = cpu_state ? false : true;
281
282 if ((mode_prev == SPLIT && mode == LOCK) && cpu_state)
283 return -EACCES;
284
285 if (mode_prev == mode)
286 return -EAGAIN;
287
288 return 0;
289}
290
Lukas Funkec6f90582022-10-28 14:15:47 +0200291static void mark_r5_used(u32 nr, u8 mode)
292{
293 u32 mask = 0;
294
295 if (mode == LOCK) {
296 mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK;
297 } else {
298 switch (nr) {
299 case ZYNQMP_CORE_RPU0:
300 mask = ZYNQMP_RPU0_USE_MASK;
301 break;
302 case ZYNQMP_CORE_RPU1:
303 mask = ZYNQMP_RPU1_USE_MASK;
304 break;
305 default:
306 return;
307 }
308 }
309 zynqmp_mmio_write((ulong)&pmu_base->gen_storage4, mask, mask);
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +0530310}
311
Simon Glassed38aef2020-05-10 11:40:03 -0600312int cpu_release(u32 nr, int argc, char *const argv[])
Michal Simek58f865f2015-04-15 13:36:40 +0200313{
Venkatesh Yadav Abbarapuae8bc3d2022-10-04 11:04:54 +0530314 if (nr <= ZYNQMP_CORE_APU3) {
Michal Simek58f865f2015-04-15 13:36:40 +0200315 u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
316 /* HIGH */
317 writel((u32)(boot_addr >> 32),
318 ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8);
319 /* LOW */
320 writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK),
321 ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
322
323 u32 val = readl(&crfapb_base->rst_fpd_apu);
324 val &= ~(1 << nr);
325 writel(val, &crfapb_base->rst_fpd_apu);
326 } else {
327 if (argc != 2) {
328 printf("Invalid number of arguments to release.\n");
329 printf("<addr> <mode>-Start addr lockstep or split\n");
330 return 1;
331 }
332
Simon Glass3ff49ec2021-07-24 09:03:29 -0600333 u32 boot_addr = hextoul(argv[0], NULL);
Michal Simekf5005ce2015-05-22 13:28:23 +0200334 u32 boot_addr_uniq = 0;
Michal Simek58f865f2015-04-15 13:36:40 +0200335 if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR ||
336 boot_addr == ZYNQMP_R5_HIVEC_ADDR)) {
Michal Simekf5005ce2015-05-22 13:28:23 +0200337 printf("Using TCM jump trampoline for address 0x%x\n",
338 boot_addr);
339 /* Save boot address for later usage */
340 boot_addr_uniq = boot_addr;
341 /*
342 * R5 needs to start from LOVEC at TCM
343 * OCM will be probably occupied by ATF
344 */
345 boot_addr = ZYNQMP_R5_LOVEC_ADDR;
Michal Simek58f865f2015-04-15 13:36:40 +0200346 }
347
Siva Durga Prasad Paladugue0a1f1e2017-08-01 16:24:52 +0530348 /*
349 * Since we don't know where the user may have loaded the image
350 * for an R5 we have to flush all the data cache to ensure
351 * the R5 sees it.
352 */
353 flush_dcache_all();
354
Padmarao Begari9ec525f2024-11-04 17:57:50 +0530355 if (!strcmp(argv[1], "lockstep") || !strcmp(argv[1], "0")) {
Venkatesh Yadav Abbarapu5824c172023-06-08 08:51:52 +0530356 if (nr != ZYNQMP_CORE_RPU0) {
357 printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n");
358 return 1;
359 }
Michal Simek58f865f2015-04-15 13:36:40 +0200360 printf("R5 lockstep mode\n");
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600361 set_r5_reset(nr, LOCK);
Michal Simek58f865f2015-04-15 13:36:40 +0200362 set_r5_tcm_mode(LOCK);
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600363 set_r5_halt_mode(nr, HALT, LOCK);
Michal Simek08adc902015-05-22 13:26:33 +0200364 set_r5_start(boot_addr);
Michal Simek58f865f2015-04-15 13:36:40 +0200365 enable_clock_r5();
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600366 release_r5_reset(nr, LOCK);
Siva Durga Prasad Paladugue0a1f1e2017-08-01 16:24:52 +0530367 dcache_disable();
Ashok Reddy Somab43d3cf2023-04-05 15:06:45 +0200368 write_tcm_boot_trampoline(nr, boot_addr_uniq);
Siva Durga Prasad Paladugue0a1f1e2017-08-01 16:24:52 +0530369 dcache_enable();
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600370 set_r5_halt_mode(nr, RELEASE, LOCK);
Lukas Funkec6f90582022-10-28 14:15:47 +0200371 mark_r5_used(nr, LOCK);
Padmarao Begari9ec525f2024-11-04 17:57:50 +0530372 } else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) {
Michal Simek58f865f2015-04-15 13:36:40 +0200373 printf("R5 split mode\n");
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600374 set_r5_reset(nr, SPLIT);
Michal Simek58f865f2015-04-15 13:36:40 +0200375 set_r5_tcm_mode(SPLIT);
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600376 set_r5_halt_mode(nr, HALT, SPLIT);
Siva Durga Prasad Paladugue0a1f1e2017-08-01 16:24:52 +0530377 set_r5_start(boot_addr);
Michal Simek58f865f2015-04-15 13:36:40 +0200378 enable_clock_r5();
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600379 release_r5_reset(nr, SPLIT);
Siva Durga Prasad Paladugue0a1f1e2017-08-01 16:24:52 +0530380 dcache_disable();
Ashok Reddy Somab43d3cf2023-04-05 15:06:45 +0200381 write_tcm_boot_trampoline(nr, boot_addr_uniq);
Siva Durga Prasad Paladugue0a1f1e2017-08-01 16:24:52 +0530382 dcache_enable();
Ashok Reddy Soma86d212e2021-04-15 05:12:15 -0600383 set_r5_halt_mode(nr, RELEASE, SPLIT);
Lukas Funkec6f90582022-10-28 14:15:47 +0200384 mark_r5_used(nr, SPLIT);
Michal Simek58f865f2015-04-15 13:36:40 +0200385 } else {
386 printf("Unsupported mode\n");
387 return 1;
388 }
389 }
390
391 return 0;
392}