Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 - 2015 Xilinx, Inc. |
| 4 | * Michal Simek <michal.simek@xilinx.com> |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 970b61e | 2019-11-14 12:57:09 -0700 | [diff] [blame] | 8 | #include <cpu_func.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 9 | #include <log.h> |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 10 | #include <asm/arch/hardware.h> |
| 11 | #include <asm/arch/sys_proto.h> |
| 12 | #include <asm/io.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 13 | #include <linux/delay.h> |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 14 | |
| 15 | #define LOCK 0 |
| 16 | #define SPLIT 1 |
| 17 | |
| 18 | #define HALT 0 |
| 19 | #define RELEASE 1 |
| 20 | |
| 21 | #define ZYNQMP_BOOTADDR_HIGH_MASK 0xFFFFFFFF |
| 22 | #define ZYNQMP_R5_HIVEC_ADDR 0xFFFF0000 |
| 23 | #define ZYNQMP_R5_LOVEC_ADDR 0x0 |
| 24 | #define ZYNQMP_RPU_CFG_CPU_HALT_MASK 0x01 |
| 25 | #define ZYNQMP_RPU_CFG_HIVEC_MASK 0x04 |
| 26 | #define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08 |
| 27 | #define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40 |
| 28 | #define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10 |
| 29 | |
| 30 | #define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04 |
| 31 | #define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK 0x01 |
| 32 | #define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02 |
| 33 | #define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 |
| 34 | |
| 35 | #define ZYNQMP_TCM_START_ADDRESS 0xFFE00000 |
| 36 | #define ZYNQMP_TCM_BOTH_SIZE 0x40000 |
| 37 | |
| 38 | #define ZYNQMP_CORE_APU0 0 |
| 39 | #define ZYNQMP_CORE_APU3 3 |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 40 | #define ZYNQMP_CORE_RPU0 4 |
| 41 | #define ZYNQMP_CORE_RPU1 5 |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 42 | |
| 43 | #define ZYNQMP_MAX_CORES 6 |
| 44 | |
| 45 | int is_core_valid(unsigned int core) |
| 46 | { |
| 47 | if (core < ZYNQMP_MAX_CORES) |
| 48 | return 1; |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | |
Michal Simek | 1669e18 | 2018-06-13 08:56:31 +0200 | [diff] [blame] | 53 | int cpu_reset(u32 nr) |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 54 | { |
| 55 | puts("Feature is not implemented.\n"); |
| 56 | return 0; |
| 57 | } |
| 58 | |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 59 | static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode) |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 60 | { |
| 61 | u32 tmp; |
| 62 | |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 63 | if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) { |
| 64 | tmp = readl(&rpu_base->rpu0_cfg); |
| 65 | if (halt == HALT) |
| 66 | tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; |
| 67 | else |
| 68 | tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; |
| 69 | writel(tmp, &rpu_base->rpu0_cfg); |
| 70 | } |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 71 | |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 72 | if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) { |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 73 | tmp = readl(&rpu_base->rpu1_cfg); |
| 74 | if (halt == HALT) |
| 75 | tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK; |
| 76 | else |
| 77 | tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK; |
| 78 | writel(tmp, &rpu_base->rpu1_cfg); |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | static void set_r5_tcm_mode(u8 mode) |
| 83 | { |
| 84 | u32 tmp; |
| 85 | |
| 86 | tmp = readl(&rpu_base->rpu_glbl_ctrl); |
| 87 | if (mode == LOCK) { |
| 88 | tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; |
| 89 | tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | |
| 90 | ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK; |
| 91 | } else { |
| 92 | tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; |
| 93 | tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK | |
| 94 | ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK); |
| 95 | } |
| 96 | |
| 97 | writel(tmp, &rpu_base->rpu_glbl_ctrl); |
| 98 | } |
| 99 | |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 100 | static void set_r5_reset(u32 nr, u8 mode) |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 101 | { |
| 102 | u32 tmp; |
| 103 | |
| 104 | tmp = readl(&crlapb_base->rst_lpd_top); |
Neal Frager | d929bbf | 2022-05-04 09:12:26 +0200 | [diff] [blame] | 105 | if (mode == LOCK) { |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 106 | tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | |
Neal Frager | d929bbf | 2022-05-04 09:12:26 +0200 | [diff] [blame] | 107 | ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK | |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 108 | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); |
Neal Frager | d929bbf | 2022-05-04 09:12:26 +0200 | [diff] [blame] | 109 | } else { |
| 110 | if (nr == ZYNQMP_CORE_RPU0) { |
| 111 | tmp |= ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK; |
| 112 | if (tmp & ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK) |
| 113 | tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK; |
| 114 | } else { |
| 115 | tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; |
| 116 | if (tmp & ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK) |
| 117 | tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK; |
| 118 | } |
| 119 | } |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 120 | |
| 121 | writel(tmp, &crlapb_base->rst_lpd_top); |
| 122 | } |
| 123 | |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 124 | static void release_r5_reset(u32 nr, u8 mode) |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 125 | { |
| 126 | u32 tmp; |
| 127 | |
| 128 | tmp = readl(&crlapb_base->rst_lpd_top); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 129 | if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) |
| 130 | tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | |
| 131 | ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 132 | |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 133 | if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) |
| 134 | tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | |
| 135 | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 136 | |
| 137 | writel(tmp, &crlapb_base->rst_lpd_top); |
| 138 | } |
| 139 | |
| 140 | static void enable_clock_r5(void) |
| 141 | { |
| 142 | u32 tmp; |
| 143 | |
| 144 | tmp = readl(&crlapb_base->cpu_r5_ctrl); |
| 145 | tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK; |
| 146 | writel(tmp, &crlapb_base->cpu_r5_ctrl); |
| 147 | |
| 148 | /* Give some delay for clock |
Robert P. J. Day | 8d56db9 | 2016-07-15 13:44:45 -0400 | [diff] [blame] | 149 | * to propagate */ |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 150 | udelay(0x500); |
| 151 | } |
| 152 | |
Neal Frager | d929bbf | 2022-05-04 09:12:26 +0200 | [diff] [blame] | 153 | static int check_r5_mode(void) |
| 154 | { |
| 155 | u32 tmp; |
| 156 | |
| 157 | tmp = readl(&rpu_base->rpu_glbl_ctrl); |
| 158 | if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK) |
| 159 | return SPLIT; |
| 160 | |
| 161 | return LOCK; |
| 162 | } |
| 163 | |
Michal Simek | 1669e18 | 2018-06-13 08:56:31 +0200 | [diff] [blame] | 164 | int cpu_disable(u32 nr) |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 165 | { |
Venkatesh Yadav Abbarapu | ae8bc3d | 2022-10-04 11:04:54 +0530 | [diff] [blame^] | 166 | if (nr <= ZYNQMP_CORE_APU3) { |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 167 | u32 val = readl(&crfapb_base->rst_fpd_apu); |
| 168 | val |= 1 << nr; |
| 169 | writel(val, &crfapb_base->rst_fpd_apu); |
| 170 | } else { |
Neal Frager | d929bbf | 2022-05-04 09:12:26 +0200 | [diff] [blame] | 171 | set_r5_reset(nr, check_r5_mode()); |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
Michal Simek | 1669e18 | 2018-06-13 08:56:31 +0200 | [diff] [blame] | 177 | int cpu_status(u32 nr) |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 178 | { |
Venkatesh Yadav Abbarapu | ae8bc3d | 2022-10-04 11:04:54 +0530 | [diff] [blame^] | 179 | if (nr <= ZYNQMP_CORE_APU3) { |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 180 | u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); |
| 181 | u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) + |
| 182 | nr * 8); |
| 183 | u32 val = readl(&crfapb_base->rst_fpd_apu); |
| 184 | val &= 1 << nr; |
| 185 | printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n", |
| 186 | nr, val ? "OFF" : "ON" , addr_high, addr_low); |
| 187 | } else { |
| 188 | u32 val = readl(&crlapb_base->rst_lpd_top); |
| 189 | val &= 1 << (nr - 4); |
| 190 | printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON"); |
| 191 | } |
| 192 | |
| 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | static void set_r5_start(u8 high) |
| 197 | { |
| 198 | u32 tmp; |
| 199 | |
| 200 | tmp = readl(&rpu_base->rpu0_cfg); |
| 201 | if (high) |
| 202 | tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK; |
| 203 | else |
| 204 | tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK; |
| 205 | writel(tmp, &rpu_base->rpu0_cfg); |
| 206 | |
| 207 | tmp = readl(&rpu_base->rpu1_cfg); |
| 208 | if (high) |
| 209 | tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK; |
| 210 | else |
| 211 | tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK; |
| 212 | writel(tmp, &rpu_base->rpu1_cfg); |
| 213 | } |
| 214 | |
Michal Simek | f5005ce | 2015-05-22 13:28:23 +0200 | [diff] [blame] | 215 | static void write_tcm_boot_trampoline(u32 boot_addr) |
| 216 | { |
| 217 | if (boot_addr) { |
| 218 | /* |
| 219 | * Boot trampoline is simple ASM code below. |
| 220 | * |
| 221 | * b over; |
| 222 | * label: |
| 223 | * .word 0 |
| 224 | * over: ldr r0, =label |
| 225 | * ldr r1, [r0] |
| 226 | * bx r1 |
| 227 | */ |
| 228 | debug("Write boot trampoline for %x\n", boot_addr); |
| 229 | writel(0xea000000, ZYNQMP_TCM_START_ADDRESS); |
| 230 | writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4); |
| 231 | writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8); |
| 232 | writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc); |
| 233 | writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10); |
| 234 | writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for |
| 235 | } |
| 236 | } |
| 237 | |
Siva Durga Prasad Paladugu | 5e2a907 | 2017-07-13 19:01:09 +0530 | [diff] [blame] | 238 | void initialize_tcm(bool mode) |
| 239 | { |
| 240 | if (!mode) { |
| 241 | set_r5_tcm_mode(LOCK); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 242 | set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK); |
Siva Durga Prasad Paladugu | 5e2a907 | 2017-07-13 19:01:09 +0530 | [diff] [blame] | 243 | enable_clock_r5(); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 244 | release_r5_reset(ZYNQMP_CORE_RPU0, LOCK); |
Siva Durga Prasad Paladugu | 5e2a907 | 2017-07-13 19:01:09 +0530 | [diff] [blame] | 245 | } else { |
| 246 | set_r5_tcm_mode(SPLIT); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 247 | set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT); |
Siva Durga Prasad Paladugu | 5e2a907 | 2017-07-13 19:01:09 +0530 | [diff] [blame] | 248 | enable_clock_r5(); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 249 | release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT); |
Siva Durga Prasad Paladugu | 5e2a907 | 2017-07-13 19:01:09 +0530 | [diff] [blame] | 250 | } |
| 251 | } |
| 252 | |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 253 | int cpu_release(u32 nr, int argc, char *const argv[]) |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 254 | { |
Venkatesh Yadav Abbarapu | ae8bc3d | 2022-10-04 11:04:54 +0530 | [diff] [blame^] | 255 | if (nr <= ZYNQMP_CORE_APU3) { |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 256 | u64 boot_addr = simple_strtoull(argv[0], NULL, 16); |
| 257 | /* HIGH */ |
| 258 | writel((u32)(boot_addr >> 32), |
| 259 | ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8); |
| 260 | /* LOW */ |
| 261 | writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK), |
| 262 | ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); |
| 263 | |
| 264 | u32 val = readl(&crfapb_base->rst_fpd_apu); |
| 265 | val &= ~(1 << nr); |
| 266 | writel(val, &crfapb_base->rst_fpd_apu); |
| 267 | } else { |
| 268 | if (argc != 2) { |
| 269 | printf("Invalid number of arguments to release.\n"); |
| 270 | printf("<addr> <mode>-Start addr lockstep or split\n"); |
| 271 | return 1; |
| 272 | } |
| 273 | |
Simon Glass | 3ff49ec | 2021-07-24 09:03:29 -0600 | [diff] [blame] | 274 | u32 boot_addr = hextoul(argv[0], NULL); |
Michal Simek | f5005ce | 2015-05-22 13:28:23 +0200 | [diff] [blame] | 275 | u32 boot_addr_uniq = 0; |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 276 | if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR || |
| 277 | boot_addr == ZYNQMP_R5_HIVEC_ADDR)) { |
Michal Simek | f5005ce | 2015-05-22 13:28:23 +0200 | [diff] [blame] | 278 | printf("Using TCM jump trampoline for address 0x%x\n", |
| 279 | boot_addr); |
| 280 | /* Save boot address for later usage */ |
| 281 | boot_addr_uniq = boot_addr; |
| 282 | /* |
| 283 | * R5 needs to start from LOVEC at TCM |
| 284 | * OCM will be probably occupied by ATF |
| 285 | */ |
| 286 | boot_addr = ZYNQMP_R5_LOVEC_ADDR; |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 287 | } |
| 288 | |
Siva Durga Prasad Paladugu | e0a1f1e | 2017-08-01 16:24:52 +0530 | [diff] [blame] | 289 | /* |
| 290 | * Since we don't know where the user may have loaded the image |
| 291 | * for an R5 we have to flush all the data cache to ensure |
| 292 | * the R5 sees it. |
| 293 | */ |
| 294 | flush_dcache_all(); |
| 295 | |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 296 | if (!strncmp(argv[1], "lockstep", 8)) { |
| 297 | printf("R5 lockstep mode\n"); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 298 | set_r5_reset(nr, LOCK); |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 299 | set_r5_tcm_mode(LOCK); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 300 | set_r5_halt_mode(nr, HALT, LOCK); |
Michal Simek | 08adc90 | 2015-05-22 13:26:33 +0200 | [diff] [blame] | 301 | set_r5_start(boot_addr); |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 302 | enable_clock_r5(); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 303 | release_r5_reset(nr, LOCK); |
Siva Durga Prasad Paladugu | e0a1f1e | 2017-08-01 16:24:52 +0530 | [diff] [blame] | 304 | dcache_disable(); |
Michal Simek | f5005ce | 2015-05-22 13:28:23 +0200 | [diff] [blame] | 305 | write_tcm_boot_trampoline(boot_addr_uniq); |
Siva Durga Prasad Paladugu | e0a1f1e | 2017-08-01 16:24:52 +0530 | [diff] [blame] | 306 | dcache_enable(); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 307 | set_r5_halt_mode(nr, RELEASE, LOCK); |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 308 | } else if (!strncmp(argv[1], "split", 5)) { |
| 309 | printf("R5 split mode\n"); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 310 | set_r5_reset(nr, SPLIT); |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 311 | set_r5_tcm_mode(SPLIT); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 312 | set_r5_halt_mode(nr, HALT, SPLIT); |
Siva Durga Prasad Paladugu | e0a1f1e | 2017-08-01 16:24:52 +0530 | [diff] [blame] | 313 | set_r5_start(boot_addr); |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 314 | enable_clock_r5(); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 315 | release_r5_reset(nr, SPLIT); |
Siva Durga Prasad Paladugu | e0a1f1e | 2017-08-01 16:24:52 +0530 | [diff] [blame] | 316 | dcache_disable(); |
Michal Simek | f5005ce | 2015-05-22 13:28:23 +0200 | [diff] [blame] | 317 | write_tcm_boot_trampoline(boot_addr_uniq); |
Siva Durga Prasad Paladugu | e0a1f1e | 2017-08-01 16:24:52 +0530 | [diff] [blame] | 318 | dcache_enable(); |
Ashok Reddy Soma | 86d212e | 2021-04-15 05:12:15 -0600 | [diff] [blame] | 319 | set_r5_halt_mode(nr, RELEASE, SPLIT); |
Michal Simek | 58f865f | 2015-04-15 13:36:40 +0200 | [diff] [blame] | 320 | } else { |
| 321 | printf("Unsupported mode\n"); |
| 322 | return 1; |
| 323 | } |
| 324 | } |
| 325 | |
| 326 | return 0; |
| 327 | } |