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Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04001/*
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +00002 * Common configuration settings for IGEP technology based boards
3 *
4 * (C) Copyright 2012
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04005 * ISEE 2007 SL, <www.iseebcn.com>
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04008 */
9
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +000010#ifndef __IGEP00X0_H
11#define __IGEP00X0_H
12
Enric Balletbò i Serraed116482013-12-06 21:30:24 +010013#define CONFIG_NR_DRAM_BANKS 2
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040014
Enric Balletbò i Serraed116482013-12-06 21:30:24 +010015#include <configs/ti_omap3_common.h>
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040016
Tom Rinicfff4aa2016-08-26 13:30:43 -040017/*
18 * We are only ever GP parts and will utilize all of the "downloaded image"
19 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
20 */
Enric Balletbo i Serra8aa10d42016-05-03 08:59:24 +020021#undef CONFIG_SPL_TEXT_BASE
Enric Balletbo i Serra8aa10d42016-05-03 08:59:24 +020022#define CONFIG_SPL_TEXT_BASE 0x40200000
23
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040024#define CONFIG_MISC_INIT_R
25
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040026#define CONFIG_REVISION_TAG 1
27
Pau Pajuelo4ddc3092017-08-17 03:09:14 +020028/* GPIO banks */
29#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */
30#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */
31
32/* TPS65950 */
33#define PBIASLITEVMODE1 (1 << 8)
34
35/* LED */
36#define IGEP0020_GPIO_LED 27
37#define IGEP0030_GPIO_LED 16
38
39/* Board and revision detection GPIOs */
40#define IGEP0030_USB_TRANSCEIVER_RESET 54
41#define GPIO_IGEP00X0_BOARD_DETECTION 28
42#define GPIO_IGEP00X0_REVISION_DETECTION 129
Javier Martinez Canillasd549ace2012-12-27 03:36:01 +000043
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040044/* USB */
Ladislav Michl06c1cd02016-01-04 23:08:01 +010045#define CONFIG_USB_MUSB_UDC 1
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040046#define CONFIG_USB_OMAP3 1
47#define CONFIG_TWL4030_USB 1
48
49/* USB device configuration */
50#define CONFIG_USB_DEVICE 1
51#define CONFIG_USB_TTY 1
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040052
53/* Change these to suit your needs */
54#define CONFIG_USBD_VENDORID 0x0451
55#define CONFIG_USBD_PRODUCTID 0x5678
56#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
57#define CONFIG_USBD_PRODUCT_NAME "IGEP"
58
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020059#ifndef CONFIG_SPL_BUILD
60
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020061/* Environment */
62#define ENV_DEVICE_SETTINGS \
63 "stdin=serial\0" \
64 "stdout=serial\0" \
65 "stderr=serial\0"
66
67#define MEM_LAYOUT_SETTINGS \
68 DEFAULT_LINUX_BOOT_ENV \
69 "scriptaddr=0x87E00000\0" \
70 "pxefile_addr_r=0x87F00000\0"
71
72#define BOOT_TARGET_DEVICES(func) \
73 func(MMC, mmc, 0)
74
Pau Pajuelo4ddc3092017-08-17 03:09:14 +020075#define CONFIG_BOOTCOMMAND \
76 "run findfdt; " \
77 "run distro_bootcmd"
78
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020079#include <config_distro_bootcmd.h>
80
Pau Pajuelo4ddc3092017-08-17 03:09:14 +020081#define ENV_FINDFDT \
82 "findfdt="\
83 "if test ${board_name} = igep0020; then " \
84 "if test ${board_rev} = F; then " \
85 "setenv fdtfile omap3-igep0020-rev-f.dtb; " \
86 "else " \
87 "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \
88 "if test ${board_name} = igep0030; then " \
89 "if test ${board_rev} = G; then " \
90 "setenv fdtfile omap3-igep0030-rev-g.dtb; " \
91 "else " \
92 "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \
93 "if test ${fdtfile} = ''; then " \
94 "echo WARNING: Could not determine device tree to use; fi; \0"
95
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040096#define CONFIG_EXTRA_ENV_SETTINGS \
Pau Pajuelo4ddc3092017-08-17 03:09:14 +020097 ENV_FINDFDT \
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020098 ENV_DEVICE_SETTINGS \
99 MEM_LAYOUT_SETTINGS \
100 BOOTENV
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -0400101
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +0200102#endif
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400103
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400104/*
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400105 * SMSC911x Ethernet
106 */
107#if defined(CONFIG_CMD_NET)
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400108#define CONFIG_SMC911X
109#define CONFIG_SMC911X_32_BIT
Ladislav Michl06c1cd02016-01-04 23:08:01 +0100110#define CONFIG_SMC911X_BASE 0x2C000000
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -0400111#endif /* (CONFIG_CMD_NET) */
112
Ladislav Michl43a60622016-07-12 20:28:32 +0200113#define CONFIG_MTD_PARTITIONS
Ladislav Michlc44e29f2016-07-12 20:28:33 +0200114#define CONFIG_SYS_MTDPARTS_RUNTIME
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000115
Ladislav Michl43a60622016-07-12 20:28:32 +0200116/* OneNAND config */
Ladislav Michl43a60622016-07-12 20:28:32 +0200117#define CONFIG_USE_ONENAND_BOARD_INIT
118#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
119#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000120
Ladislav Michl43a60622016-07-12 20:28:32 +0200121/* NAND config */
Stefano Babic0cd41182015-07-26 15:18:15 +0200122#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000123#define CONFIG_SYS_NAND_5_ADDR_CYCLE
124#define CONFIG_SYS_NAND_PAGE_COUNT 64
125#define CONFIG_SYS_NAND_PAGE_SIZE 2048
126#define CONFIG_SYS_NAND_OOBSIZE 64
127#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +0200128#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
129#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
130 10, 11, 12, 13, 14, 15, 16, 17, \
131 18, 19, 20, 21, 22, 23, 24, 25, \
132 26, 27, 28, 29, 30, 31, 32, 33, \
133 34, 35, 36, 37, 38, 39, 40, 41, \
134 42, 43, 44, 45, 46, 47, 48, 49, \
135 50, 51, 52, 53, 54, 55, 56, 57, }
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000136#define CONFIG_SYS_NAND_ECCSIZE 512
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +0200137#define CONFIG_SYS_NAND_ECCBYTES 14
138#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
139#define CONFIG_NAND_OMAP_GPMC
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +0200140
Ladislav Michl43a60622016-07-12 20:28:32 +0200141/* UBI configuration */
142#define CONFIG_SPL_UBI 1
143#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
144#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
145#define CONFIG_SPL_UBI_MAX_PEBS 4096
146#define CONFIG_SPL_UBI_VOL_IDS 8
147#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
148#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3
149#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4
150#define CONFIG_SPL_UBI_PEB_OFFSET 4
151#define CONFIG_SPL_UBI_VID_OFFSET 512
152#define CONFIG_SPL_UBI_LEB_START 2048
153#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
154
155/* environment organization */
Ladislav Michl43a60622016-07-12 20:28:32 +0200156#define CONFIG_ENV_UBI_PART "UBI"
157#define CONFIG_ENV_UBI_VOLUME "config"
158#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
159#define CONFIG_UBI_SILENCE_MSG 1
160#define CONFIG_UBIFS_SILENCE_MSG 1
161#define CONFIG_ENV_SIZE (32*1024)
162
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +0000163#endif /* __IGEP00X0_H */