Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 1 | /* |
Enric Balletbò i Serra | 19f9df8 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 2 | * Common configuration settings for IGEP technology based boards |
| 3 | * |
| 4 | * (C) Copyright 2012 |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 5 | * ISEE 2007 SL, <www.iseebcn.com> |
| 6 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 8 | */ |
| 9 | |
Enric Balletbò i Serra | 19f9df8 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 10 | #ifndef __IGEP00X0_H |
| 11 | #define __IGEP00X0_H |
| 12 | |
Enric Balletbò i Serra | ed11648 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 13 | #define CONFIG_NR_DRAM_BANKS 2 |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 14 | |
Enric Balletbò i Serra | ed11648 | 2013-12-06 21:30:24 +0100 | [diff] [blame] | 15 | #include <configs/ti_omap3_common.h> |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 16 | |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 17 | /* |
| 18 | * We are only ever GP parts and will utilize all of the "downloaded image" |
| 19 | * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). |
| 20 | */ |
Enric Balletbo i Serra | 8aa10d4 | 2016-05-03 08:59:24 +0200 | [diff] [blame] | 21 | #undef CONFIG_SPL_TEXT_BASE |
Enric Balletbo i Serra | 8aa10d4 | 2016-05-03 08:59:24 +0200 | [diff] [blame] | 22 | #define CONFIG_SPL_TEXT_BASE 0x40200000 |
| 23 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 24 | #define CONFIG_MISC_INIT_R |
| 25 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 26 | #define CONFIG_REVISION_TAG 1 |
| 27 | |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 28 | /* GPIO banks */ |
| 29 | #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */ |
| 30 | #define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */ |
| 31 | |
| 32 | /* TPS65950 */ |
| 33 | #define PBIASLITEVMODE1 (1 << 8) |
| 34 | |
| 35 | /* LED */ |
| 36 | #define IGEP0020_GPIO_LED 27 |
| 37 | #define IGEP0030_GPIO_LED 16 |
| 38 | |
| 39 | /* Board and revision detection GPIOs */ |
| 40 | #define IGEP0030_USB_TRANSCEIVER_RESET 54 |
| 41 | #define GPIO_IGEP00X0_BOARD_DETECTION 28 |
| 42 | #define GPIO_IGEP00X0_REVISION_DETECTION 129 |
Javier Martinez Canillas | d549ace | 2012-12-27 03:36:01 +0000 | [diff] [blame] | 43 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 44 | /* USB */ |
Ladislav Michl | 06c1cd0 | 2016-01-04 23:08:01 +0100 | [diff] [blame] | 45 | #define CONFIG_USB_MUSB_UDC 1 |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 46 | #define CONFIG_USB_OMAP3 1 |
| 47 | #define CONFIG_TWL4030_USB 1 |
| 48 | |
| 49 | /* USB device configuration */ |
| 50 | #define CONFIG_USB_DEVICE 1 |
| 51 | #define CONFIG_USB_TTY 1 |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 52 | |
| 53 | /* Change these to suit your needs */ |
| 54 | #define CONFIG_USBD_VENDORID 0x0451 |
| 55 | #define CONFIG_USBD_PRODUCTID 0x5678 |
| 56 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" |
| 57 | #define CONFIG_USBD_PRODUCT_NAME "IGEP" |
| 58 | |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 59 | #ifndef CONFIG_SPL_BUILD |
| 60 | |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 61 | /* Environment */ |
| 62 | #define ENV_DEVICE_SETTINGS \ |
| 63 | "stdin=serial\0" \ |
| 64 | "stdout=serial\0" \ |
| 65 | "stderr=serial\0" |
| 66 | |
| 67 | #define MEM_LAYOUT_SETTINGS \ |
| 68 | DEFAULT_LINUX_BOOT_ENV \ |
| 69 | "scriptaddr=0x87E00000\0" \ |
| 70 | "pxefile_addr_r=0x87F00000\0" |
| 71 | |
| 72 | #define BOOT_TARGET_DEVICES(func) \ |
| 73 | func(MMC, mmc, 0) |
| 74 | |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 75 | #define CONFIG_BOOTCOMMAND \ |
| 76 | "run findfdt; " \ |
| 77 | "run distro_bootcmd" |
| 78 | |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 79 | #include <config_distro_bootcmd.h> |
| 80 | |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 81 | #define ENV_FINDFDT \ |
| 82 | "findfdt="\ |
| 83 | "if test ${board_name} = igep0020; then " \ |
| 84 | "if test ${board_rev} = F; then " \ |
| 85 | "setenv fdtfile omap3-igep0020-rev-f.dtb; " \ |
| 86 | "else " \ |
| 87 | "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \ |
| 88 | "if test ${board_name} = igep0030; then " \ |
| 89 | "if test ${board_rev} = G; then " \ |
| 90 | "setenv fdtfile omap3-igep0030-rev-g.dtb; " \ |
| 91 | "else " \ |
| 92 | "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \ |
| 93 | "if test ${fdtfile} = ''; then " \ |
| 94 | "echo WARNING: Could not determine device tree to use; fi; \0" |
| 95 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 96 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Pau Pajuelo | 4ddc309 | 2017-08-17 03:09:14 +0200 | [diff] [blame] | 97 | ENV_FINDFDT \ |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 98 | ENV_DEVICE_SETTINGS \ |
| 99 | MEM_LAYOUT_SETTINGS \ |
| 100 | BOOTENV |
Enric Balletbo i Serra | 4adf801 | 2011-04-19 09:16:36 -0400 | [diff] [blame] | 101 | |
Enric Balletbò i Serra | a5d75f7 | 2015-09-07 08:28:09 +0200 | [diff] [blame] | 102 | #endif |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 103 | |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 104 | /* |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 105 | * SMSC911x Ethernet |
| 106 | */ |
| 107 | #if defined(CONFIG_CMD_NET) |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 108 | #define CONFIG_SMC911X |
| 109 | #define CONFIG_SMC911X_32_BIT |
Ladislav Michl | 06c1cd0 | 2016-01-04 23:08:01 +0100 | [diff] [blame] | 110 | #define CONFIG_SMC911X_BASE 0x2C000000 |
Enric Balletbo i Serra | 2ce268c | 2010-10-14 16:54:59 -0400 | [diff] [blame] | 111 | #endif /* (CONFIG_CMD_NET) */ |
| 112 | |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 113 | #define CONFIG_MTD_PARTITIONS |
Ladislav Michl | c44e29f | 2016-07-12 20:28:33 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_MTDPARTS_RUNTIME |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 115 | |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 116 | /* OneNAND config */ |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 117 | #define CONFIG_USE_ONENAND_BOARD_INIT |
| 118 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
| 119 | #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 120 | |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 121 | /* NAND config */ |
Stefano Babic | 0cd4118 | 2015-07-26 15:18:15 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 123 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 124 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 125 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
| 126 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 127 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) |
Ladislav Michl | 8ed5b0b | 2015-10-12 18:09:14 +0200 | [diff] [blame] | 128 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS |
| 129 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ |
| 130 | 10, 11, 12, 13, 14, 15, 16, 17, \ |
| 131 | 18, 19, 20, 21, 22, 23, 24, 25, \ |
| 132 | 26, 27, 28, 29, 30, 31, 32, 33, \ |
| 133 | 34, 35, 36, 37, 38, 39, 40, 41, \ |
| 134 | 42, 43, 44, 45, 46, 47, 48, 49, \ |
| 135 | 50, 51, 52, 53, 54, 55, 56, 57, } |
Javier Martinez Canillas | 361fc83 | 2012-07-28 01:19:34 +0000 | [diff] [blame] | 136 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
Ladislav Michl | 8ed5b0b | 2015-10-12 18:09:14 +0200 | [diff] [blame] | 137 | #define CONFIG_SYS_NAND_ECCBYTES 14 |
| 138 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |
| 139 | #define CONFIG_NAND_OMAP_GPMC |
Ladislav Michl | 8ed5b0b | 2015-10-12 18:09:14 +0200 | [diff] [blame] | 140 | |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 141 | /* UBI configuration */ |
| 142 | #define CONFIG_SPL_UBI 1 |
| 143 | #define CONFIG_SPL_UBI_MAX_VOL_LEBS 256 |
| 144 | #define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024) |
| 145 | #define CONFIG_SPL_UBI_MAX_PEBS 4096 |
| 146 | #define CONFIG_SPL_UBI_VOL_IDS 8 |
| 147 | #define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0 |
| 148 | #define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3 |
| 149 | #define CONFIG_SPL_UBI_LOAD_ARGS_ID 4 |
| 150 | #define CONFIG_SPL_UBI_PEB_OFFSET 4 |
| 151 | #define CONFIG_SPL_UBI_VID_OFFSET 512 |
| 152 | #define CONFIG_SPL_UBI_LEB_START 2048 |
| 153 | #define CONFIG_SPL_UBI_INFO_ADDR 0x88080000 |
| 154 | |
| 155 | /* environment organization */ |
Ladislav Michl | 43a6062 | 2016-07-12 20:28:32 +0200 | [diff] [blame] | 156 | #define CONFIG_ENV_UBI_PART "UBI" |
| 157 | #define CONFIG_ENV_UBI_VOLUME "config" |
| 158 | #define CONFIG_ENV_UBI_VOLUME_REDUND "config_r" |
| 159 | #define CONFIG_UBI_SILENCE_MSG 1 |
| 160 | #define CONFIG_UBIFS_SILENCE_MSG 1 |
| 161 | #define CONFIG_ENV_SIZE (32*1024) |
| 162 | |
Enric Balletbò i Serra | 19f9df8 | 2012-03-05 11:32:16 +0000 | [diff] [blame] | 163 | #endif /* __IGEP00X0_H */ |