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wdenkf8062712005-01-09 23:16:25 +00001/*
2 * Basic I2C functions
3 *
4 * Copyright (c) 2004 Texas Instruments
5 *
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15 *
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
18 *
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20 *
Lubomir Popov4d98efd2013-06-01 06:44:38 +000021 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24 * OMAPs and derivatives as well. The only anticipated exception would
25 * be the OMAP2420, which shall require driver modification.
26 * - Rewritten i2c_read to operate correctly with all types of chips
27 * (old function could not read consistent data from some I2C slaves).
28 * - Optimized i2c_write.
29 * - New i2c_probe, performs write access vs read. The old probe could
30 * hang the system under certain conditions (e.g. unconfigured pads).
31 * - The read/write/probe functions try to identify unconfigured bus.
32 * - Status functions now read irqstatus_raw as per TRM guidelines
33 * (except for OMAP243X and OMAP34XX).
34 * - Driver now supports up to I2C5 (OMAP5).
Hannes Petermaierd5885052014-02-03 21:22:18 +010035 *
Hannes Schmelzer7935f032015-05-28 15:41:12 +020036 * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
Hannes Petermaierd5885052014-02-03 21:22:18 +010037 * - Added support for set_speed
38 *
wdenkf8062712005-01-09 23:16:25 +000039 */
40
41#include <common.h>
Mugunthan V N560037b2016-07-18 15:11:01 +053042#include <dm.h>
Heiko Schocherf53f2b82013-10-22 11:03:18 +020043#include <i2c.h>
wdenkcb99da52005-01-12 00:15:14 +000044
wdenkf8062712005-01-09 23:16:25 +000045#include <asm/arch/i2c.h>
46#include <asm/io.h>
47
Steve Sakoman10acc712010-06-12 06:42:57 -070048#include "omap24xx_i2c.h"
49
John Rigby0d21ed02010-12-20 18:27:51 -070050DECLARE_GLOBAL_DATA_PTR;
51
Tom Rini49fbf672012-02-20 18:49:16 +000052#define I2C_TIMEOUT 1000
Steve Sakomane2bdc132010-07-19 20:31:55 -070053
Lubomir Popov4d98efd2013-06-01 06:44:38 +000054/* Absolutely safe for status update at 100 kHz I2C: */
55#define I2C_WAIT 200
56
Mugunthan V N560037b2016-07-18 15:11:01 +053057struct omap_i2c {
58 struct udevice *clk;
59 struct i2c *regs;
60 unsigned int speed;
61 int waitdelay;
62 int clk_id;
63};
64
Hannes Petermaierd5885052014-02-03 21:22:18 +010065static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
wdenkf8062712005-01-09 23:16:25 +000066{
Lukasz Majewski698a9ba2017-03-15 16:59:23 +010067 unsigned long internal_clk = 0, fclk;
68 unsigned int prescaler;
Tom Rix03b2a742009-06-28 12:52:27 -050069
Hannes Petermaierd5885052014-02-03 21:22:18 +010070 /*
Lukasz Majewski698a9ba2017-03-15 16:59:23 +010071 * This method is only called for Standard and Fast Mode speeds
72 *
73 * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
74 * page 5685, Table 24-7)
75 * that the internal I2C clock (after prescaler) should be between
76 * 7-12 MHz (at least for Fast Mode (FS)).
77 *
78 * Such approach is used in v4.9 Linux kernel in:
79 * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
Hannes Petermaierd5885052014-02-03 21:22:18 +010080 */
Tom Rix03b2a742009-06-28 12:52:27 -050081
Lukasz Majewski698a9ba2017-03-15 16:59:23 +010082 speed /= 1000; /* convert speed to kHz */
Hannes Petermaierd5885052014-02-03 21:22:18 +010083
Lukasz Majewski698a9ba2017-03-15 16:59:23 +010084 if (speed > 100)
85 internal_clk = 9600;
86 else
87 internal_clk = 4000;
Hannes Petermaierd5885052014-02-03 21:22:18 +010088
Lukasz Majewski698a9ba2017-03-15 16:59:23 +010089 fclk = I2C_IP_CLK / 1000;
90 prescaler = fclk / internal_clk;
91 prescaler = prescaler - 1;
92
93 if (speed > 100) {
94 unsigned long scl;
95
96 /* Fast mode */
97 scl = internal_clk / speed;
98 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
99 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
100 } else {
101 /* Standard mode */
102 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
103 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
Tom Rix03b2a742009-06-28 12:52:27 -0500104 }
Lukasz Majewski698a9ba2017-03-15 16:59:23 +0100105
106 debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
107 __func__, speed, prescaler, *pscl, *psch);
108
109 if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
110 return -EINVAL;
111
112 return prescaler;
Hannes Petermaierd5885052014-02-03 21:22:18 +0100113}
Mugunthan V N38d943a2016-07-18 15:11:00 +0530114
115/*
116 * Wait for the bus to be free by checking the Bus Busy (BB)
117 * bit to become clear
118 */
119static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
Hannes Petermaierd5885052014-02-03 21:22:18 +0100120{
Mugunthan V N38d943a2016-07-18 15:11:00 +0530121 int timeout = I2C_TIMEOUT;
122 u16 stat;
123
124 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
Tom Rini0670cac2017-05-12 22:33:15 -0400125#if defined(CONFIG_OMAP34XX)
Mugunthan V N38d943a2016-07-18 15:11:00 +0530126 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
127#else
128 /* Read RAW status */
129 while ((stat = readw(&i2c_base->irqstatus_raw) &
130 I2C_STAT_BB) && timeout--) {
131#endif
132 writew(stat, &i2c_base->stat);
133 udelay(waitdelay);
134 }
135
136 if (timeout <= 0) {
137 printf("Timed out in wait_for_bb: status=%04x\n",
138 stat);
139 return 1;
140 }
141 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
142 return 0;
143}
144
145/*
146 * Wait for the I2C controller to complete current action
147 * and update status
148 */
149static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
150{
151 u16 status;
152 int timeout = I2C_TIMEOUT;
153
154 do {
155 udelay(waitdelay);
Tom Rini0670cac2017-05-12 22:33:15 -0400156#if defined(CONFIG_OMAP34XX)
Mugunthan V N38d943a2016-07-18 15:11:00 +0530157 status = readw(&i2c_base->stat);
158#else
159 /* Read RAW status */
160 status = readw(&i2c_base->irqstatus_raw);
161#endif
162 } while (!(status &
163 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
164 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
165 I2C_STAT_AL)) && timeout--);
166
167 if (timeout <= 0) {
168 printf("Timed out in wait_for_event: status=%04x\n",
169 status);
170 /*
171 * If status is still 0 here, probably the bus pads have
172 * not been configured for I2C, and/or pull-ups are missing.
173 */
174 printf("Check if pads/pull-ups of bus are properly configured\n");
175 writew(0xFFFF, &i2c_base->stat);
176 status = 0;
177 }
178
179 return status;
180}
181
182static void flush_fifo(struct i2c *i2c_base)
183{
184 u16 stat;
185
186 /*
187 * note: if you try and read data when its not there or ready
188 * you get a bus error
189 */
190 while (1) {
191 stat = readw(&i2c_base->stat);
192 if (stat == I2C_STAT_RRDY) {
193 readb(&i2c_base->data);
194 writew(I2C_STAT_RRDY, &i2c_base->stat);
195 udelay(1000);
196 } else
197 break;
198 }
199}
200
201static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
202 int *waitdelay)
203{
Hannes Petermaierd5885052014-02-03 21:22:18 +0100204 int psc, fsscll = 0, fssclh = 0;
205 int hsscll = 0, hssclh = 0;
206 u32 scll = 0, sclh = 0;
Tom Rix03b2a742009-06-28 12:52:27 -0500207
Hannes Petermaierd5885052014-02-03 21:22:18 +0100208 if (speed >= OMAP_I2C_HIGH_SPEED) {
Tom Rix03b2a742009-06-28 12:52:27 -0500209 /* High speed */
Hannes Petermaierd5885052014-02-03 21:22:18 +0100210 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
211 psc -= 1;
212 if (psc < I2C_PSC_MIN) {
213 printf("Error : I2C unsupported prescaler %d\n", psc);
214 return -1;
215 }
Tom Rix03b2a742009-06-28 12:52:27 -0500216
217 /* For first phase of HS mode */
Hannes Petermaierd5885052014-02-03 21:22:18 +0100218 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
219
220 fssclh = fsscll;
Tom Rix03b2a742009-06-28 12:52:27 -0500221
222 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
223 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
224 if (((fsscll < 0) || (fssclh < 0)) ||
225 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müllera30293f2012-01-04 15:26:19 +0000226 puts("Error : I2C initializing first phase clock\n");
Hannes Petermaierd5885052014-02-03 21:22:18 +0100227 return -1;
Tom Rix03b2a742009-06-28 12:52:27 -0500228 }
229
230 /* For second phase of HS mode */
231 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
232
233 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
234 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
235 if (((fsscll < 0) || (fssclh < 0)) ||
236 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müllera30293f2012-01-04 15:26:19 +0000237 puts("Error : I2C initializing second phase clock\n");
Hannes Petermaierd5885052014-02-03 21:22:18 +0100238 return -1;
Tom Rix03b2a742009-06-28 12:52:27 -0500239 }
240
241 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
242 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
243
244 } else {
245 /* Standard and fast speed */
Hannes Petermaierd5885052014-02-03 21:22:18 +0100246 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
247 if (0 > psc) {
Andreas Müllera30293f2012-01-04 15:26:19 +0000248 puts("Error : I2C initializing clock\n");
Hannes Petermaierd5885052014-02-03 21:22:18 +0100249 return -1;
Tom Rix03b2a742009-06-28 12:52:27 -0500250 }
Tom Rix03b2a742009-06-28 12:52:27 -0500251 }
wdenkf8062712005-01-09 23:16:25 +0000252
Mugunthan V N38d943a2016-07-18 15:11:00 +0530253 *waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
Hannes Petermaierd5885052014-02-03 21:22:18 +0100254 writew(0, &i2c_base->con);
255 writew(psc, &i2c_base->psc);
256 writew(scll, &i2c_base->scll);
257 writew(sclh, &i2c_base->sclh);
258 writew(I2C_CON_EN, &i2c_base->con);
259 writew(0xFFFF, &i2c_base->stat); /* clear all pending status */
260
261 return 0;
262}
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200263
Mugunthan V N38d943a2016-07-18 15:11:00 +0530264static void omap24_i2c_deblock(struct i2c *i2c_base)
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200265{
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200266 int i;
267 u16 systest;
268 u16 orgsystest;
269
270 /* set test mode ST_EN = 1 */
271 orgsystest = readw(&i2c_base->systest);
272 systest = orgsystest;
273 /* enable testmode */
274 systest |= I2C_SYSTEST_ST_EN;
275 writew(systest, &i2c_base->systest);
276 systest &= ~I2C_SYSTEST_TMODE_MASK;
277 systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
278 writew(systest, &i2c_base->systest);
279
280 /* set SCL, SDA = 1 */
281 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
282 writew(systest, &i2c_base->systest);
283 udelay(10);
284
285 /* toggle scl 9 clocks */
286 for (i = 0; i < 9; i++) {
287 /* SCL = 0 */
288 systest &= ~I2C_SYSTEST_SCL_O;
289 writew(systest, &i2c_base->systest);
290 udelay(10);
291 /* SCL = 1 */
292 systest |= I2C_SYSTEST_SCL_O;
293 writew(systest, &i2c_base->systest);
294 udelay(10);
295 }
296
297 /* send stop */
298 systest &= ~I2C_SYSTEST_SDA_O;
299 writew(systest, &i2c_base->systest);
300 udelay(10);
301 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
302 writew(systest, &i2c_base->systest);
303 udelay(10);
304
305 /* restore original mode */
306 writew(orgsystest, &i2c_base->systest);
307}
308
Mugunthan V N38d943a2016-07-18 15:11:00 +0530309static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
310 int *waitdelay)
Hannes Petermaierd5885052014-02-03 21:22:18 +0100311{
Hannes Petermaierd5885052014-02-03 21:22:18 +0100312 int timeout = I2C_TIMEOUT;
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200313 int deblock = 1;
Hannes Petermaierd5885052014-02-03 21:22:18 +0100314
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200315retry:
Michael Jones4db67862011-07-27 14:01:55 -0400316 if (readw(&i2c_base->con) & I2C_CON_EN) {
317 writew(0, &i2c_base->con);
318 udelay(50000);
wdenkf8062712005-01-09 23:16:25 +0000319 }
320
Tom Rini49fbf672012-02-20 18:49:16 +0000321 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
322 udelay(1000);
323
324 writew(I2C_CON_EN, &i2c_base->con);
325 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
326 if (timeout <= 0) {
327 puts("ERROR: Timeout in soft-reset\n");
328 return;
329 }
330 udelay(1000);
331 }
332
Mugunthan V N38d943a2016-07-18 15:11:00 +0530333 if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) {
Hannes Petermaierd5885052014-02-03 21:22:18 +0100334 printf("ERROR: failed to setup I2C bus-speed!\n");
335 return;
336 }
Tom Rix03b2a742009-06-28 12:52:27 -0500337
wdenkf8062712005-01-09 23:16:25 +0000338 /* own address */
Michael Jones4db67862011-07-27 14:01:55 -0400339 writew(slaveadd, &i2c_base->oa);
Hannes Petermaierd5885052014-02-03 21:22:18 +0100340
Tom Rini0670cac2017-05-12 22:33:15 -0400341#if defined(CONFIG_OMAP34XX)
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000342 /*
343 * Have to enable interrupts for OMAP2/3, these IPs don't have
344 * an 'irqstatus_raw' register and we shall have to poll 'stat'
345 */
Michael Jones4db67862011-07-27 14:01:55 -0400346 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000347 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
348#endif
Michael Jones4db67862011-07-27 14:01:55 -0400349 udelay(1000);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530350 flush_fifo(i2c_base);
Michael Jones4db67862011-07-27 14:01:55 -0400351 writew(0xFFFF, &i2c_base->stat);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200352
353 /* Handle possible failed I2C state */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530354 if (wait_for_bb(i2c_base, *waitdelay))
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200355 if (deblock == 1) {
Mugunthan V N38d943a2016-07-18 15:11:00 +0530356 omap24_i2c_deblock(i2c_base);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200357 deblock = 0;
358 goto retry;
359 }
wdenkf8062712005-01-09 23:16:25 +0000360}
361
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000362/*
363 * i2c_probe: Use write access. Allows to identify addresses that are
364 * write-only (like the config register of dual-port EEPROMs)
365 */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530366static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
wdenkf8062712005-01-09 23:16:25 +0000367{
Tom Rini49fbf672012-02-20 18:49:16 +0000368 u16 status;
wdenkf8062712005-01-09 23:16:25 +0000369 int res = 1; /* default = fail */
370
Michael Jones4db67862011-07-27 14:01:55 -0400371 if (chip == readw(&i2c_base->oa))
wdenkf8062712005-01-09 23:16:25 +0000372 return res;
wdenkf8062712005-01-09 23:16:25 +0000373
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000374 /* Wait until bus is free */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530375 if (wait_for_bb(i2c_base, waitdelay))
Vincent Stehlé33205e32012-12-03 05:23:16 +0000376 return res;
wdenkf8062712005-01-09 23:16:25 +0000377
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000378 /* No data transfer, slave addr only */
Michael Jones4db67862011-07-27 14:01:55 -0400379 writew(chip, &i2c_base->sa);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000380 /* Stop bit needed here */
381 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
382 I2C_CON_STP, &i2c_base->con);
Nick Thompson48f7ae42011-04-11 22:37:41 +0000383
Mugunthan V N38d943a2016-07-18 15:11:00 +0530384 status = wait_for_event(i2c_base, waitdelay);
Vincent Stehlé33205e32012-12-03 05:23:16 +0000385
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000386 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
387 /*
388 * With current high-level command implementation, notifying
389 * the user shall flood the console with 127 messages. If
390 * silent exit is desired upon unconfigured bus, remove the
391 * following 'if' section:
392 */
393 if (status == I2C_STAT_XRDY)
Mugunthan V N38d943a2016-07-18 15:11:00 +0530394 printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
395 status);
Vincent Stehlé33205e32012-12-03 05:23:16 +0000396
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000397 goto pr_exit;
Tom Rini27eed8b2012-05-21 06:46:29 +0000398 }
Tom Rini49fbf672012-02-20 18:49:16 +0000399
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000400 /* Check for ACK (!NAK) */
401 if (!(status & I2C_STAT_NACK)) {
Hannes Petermaierd5885052014-02-03 21:22:18 +0100402 res = 0; /* Device found */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530403 udelay(waitdelay);/* Required by AM335X in SPL */
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000404 /* Abort transfer (force idle state) */
405 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
406 udelay(1000);
407 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
408 I2C_CON_STP, &i2c_base->con); /* STP */
409 }
410pr_exit:
Mugunthan V N38d943a2016-07-18 15:11:00 +0530411 flush_fifo(i2c_base);
Dirk Behme7a8f6572009-11-02 20:36:26 +0100412 writew(0xFFFF, &i2c_base->stat);
wdenkf8062712005-01-09 23:16:25 +0000413 return res;
414}
415
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000416/*
417 * i2c_read: Function now uses a single I2C read transaction with bulk transfer
418 * of the requested number of bytes (note that the 'i2c md' command
419 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
420 * defined in the board config header, this transaction shall be with
421 * Repeated Start (Sr) between the address and data phases; otherwise
422 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
423 * The address (reg offset) may be 0, 1 or 2 bytes long.
424 * Function now reads correctly from chips that return more than one
425 * byte of data per addressed register (like TI temperature sensors),
426 * or that do not need a register address at all (such as some clock
427 * distributors).
428 */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530429static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
430 uint addr, int alen, uchar *buffer, int len)
wdenkf8062712005-01-09 23:16:25 +0000431{
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000432 int i2c_error = 0;
433 u16 status;
434
435 if (alen < 0) {
436 puts("I2C read: addr len < 0\n");
437 return 1;
438 }
439 if (len < 0) {
440 puts("I2C read: data len < 0\n");
441 return 1;
442 }
443 if (buffer == NULL) {
444 puts("I2C read: NULL pointer passed\n");
445 return 1;
446 }
wdenkf8062712005-01-09 23:16:25 +0000447
Ilya Yanokbe6c2e42012-06-08 03:12:09 +0000448 if (alen > 2) {
Tom Rini49fbf672012-02-20 18:49:16 +0000449 printf("I2C read: addr len %d not supported\n", alen);
wdenkf8062712005-01-09 23:16:25 +0000450 return 1;
451 }
452
Ilya Yanokbe6c2e42012-06-08 03:12:09 +0000453 if (addr + len > (1 << 16)) {
Tom Rini49fbf672012-02-20 18:49:16 +0000454 puts("I2C read: address out of range\n");
wdenkf8062712005-01-09 23:16:25 +0000455 return 1;
456 }
457
Guy Thouret51c27272016-03-11 16:23:41 +0000458#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
459 /*
460 * EEPROM chips that implement "address overflow" are ones
461 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
462 * address and the extra bits end up in the "chip address"
463 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
464 * four 256 byte chips.
465 *
466 * Note that we consider the length of the address field to
467 * still be one byte because the extra address bits are
468 * hidden in the chip address.
469 */
470 if (alen > 0)
471 chip |= ((addr >> (alen * 8)) &
472 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
473#endif
474
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000475 /* Wait until bus not busy */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530476 if (wait_for_bb(i2c_base, waitdelay))
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000477 return 1;
478
479 /* Zero, one or two bytes reg address (offset) */
480 writew(alen, &i2c_base->cnt);
481 /* Set slave address */
482 writew(chip, &i2c_base->sa);
483
484 if (alen) {
485 /* Must write reg offset first */
486#ifdef CONFIG_I2C_REPEATED_START
487 /* No stop bit, use Repeated Start (Sr) */
488 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
489 I2C_CON_TRX, &i2c_base->con);
490#else
491 /* Stop - Start (P-S) */
492 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
493 I2C_CON_TRX, &i2c_base->con);
494#endif
495 /* Send register offset */
496 while (1) {
Mugunthan V N38d943a2016-07-18 15:11:00 +0530497 status = wait_for_event(i2c_base, waitdelay);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000498 /* Try to identify bus that is not padconf'd for I2C */
499 if (status == I2C_STAT_XRDY) {
500 i2c_error = 2;
Mugunthan V N38d943a2016-07-18 15:11:00 +0530501 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
502 status);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000503 goto rd_exit;
504 }
Hannes Petermaierd5885052014-02-03 21:22:18 +0100505 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000506 i2c_error = 1;
507 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
508 status);
509 goto rd_exit;
510 }
511 if (alen) {
512 if (status & I2C_STAT_XRDY) {
513 alen--;
514 /* Do we have to use byte access? */
515 writeb((addr >> (8 * alen)) & 0xff,
516 &i2c_base->data);
517 writew(I2C_STAT_XRDY, &i2c_base->stat);
518 }
519 }
520 if (status & I2C_STAT_ARDY) {
521 writew(I2C_STAT_ARDY, &i2c_base->stat);
522 break;
523 }
wdenkf8062712005-01-09 23:16:25 +0000524 }
525 }
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000526 /* Set slave address */
527 writew(chip, &i2c_base->sa);
528 /* Read len bytes from slave */
529 writew(len, &i2c_base->cnt);
530 /* Need stop bit here */
531 writew(I2C_CON_EN | I2C_CON_MST |
532 I2C_CON_STT | I2C_CON_STP,
533 &i2c_base->con);
wdenkf8062712005-01-09 23:16:25 +0000534
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000535 /* Receive data */
536 while (1) {
Mugunthan V N38d943a2016-07-18 15:11:00 +0530537 status = wait_for_event(i2c_base, waitdelay);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000538 /*
539 * Try to identify bus that is not padconf'd for I2C. This
540 * state could be left over from previous transactions if
541 * the address phase is skipped due to alen=0.
542 */
543 if (status == I2C_STAT_XRDY) {
544 i2c_error = 2;
Mugunthan V N38d943a2016-07-18 15:11:00 +0530545 printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
546 status);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000547 goto rd_exit;
548 }
Hannes Petermaierd5885052014-02-03 21:22:18 +0100549 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000550 i2c_error = 1;
551 goto rd_exit;
552 }
553 if (status & I2C_STAT_RRDY) {
554 *buffer++ = readb(&i2c_base->data);
555 writew(I2C_STAT_RRDY, &i2c_base->stat);
556 }
557 if (status & I2C_STAT_ARDY) {
558 writew(I2C_STAT_ARDY, &i2c_base->stat);
559 break;
560 }
561 }
562
563rd_exit:
Mugunthan V N38d943a2016-07-18 15:11:00 +0530564 flush_fifo(i2c_base);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000565 writew(0xFFFF, &i2c_base->stat);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000566 return i2c_error;
wdenkf8062712005-01-09 23:16:25 +0000567}
568
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000569/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530570static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
571 uint addr, int alen, uchar *buffer, int len)
wdenkf8062712005-01-09 23:16:25 +0000572{
Tom Rini49fbf672012-02-20 18:49:16 +0000573 int i;
574 u16 status;
575 int i2c_error = 0;
Hannes Petermaierd5885052014-02-03 21:22:18 +0100576 int timeout = I2C_TIMEOUT;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000577
578 if (alen < 0) {
579 puts("I2C write: addr len < 0\n");
580 return 1;
581 }
582
583 if (len < 0) {
584 puts("I2C write: data len < 0\n");
585 return 1;
586 }
587
588 if (buffer == NULL) {
589 puts("I2C write: NULL pointer passed\n");
590 return 1;
591 }
wdenkf8062712005-01-09 23:16:25 +0000592
Ilya Yanokbe6c2e42012-06-08 03:12:09 +0000593 if (alen > 2) {
Tom Rini49fbf672012-02-20 18:49:16 +0000594 printf("I2C write: addr len %d not supported\n", alen);
wdenkf8062712005-01-09 23:16:25 +0000595 return 1;
Tom Rini49fbf672012-02-20 18:49:16 +0000596 }
wdenkf8062712005-01-09 23:16:25 +0000597
Ilya Yanokbe6c2e42012-06-08 03:12:09 +0000598 if (addr + len > (1 << 16)) {
Tom Rini49fbf672012-02-20 18:49:16 +0000599 printf("I2C write: address 0x%x + 0x%x out of range\n",
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000600 addr, len);
wdenkf8062712005-01-09 23:16:25 +0000601 return 1;
602 }
603
Guy Thouret51c27272016-03-11 16:23:41 +0000604#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
605 /*
606 * EEPROM chips that implement "address overflow" are ones
607 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
608 * address and the extra bits end up in the "chip address"
609 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
610 * four 256 byte chips.
611 *
612 * Note that we consider the length of the address field to
613 * still be one byte because the extra address bits are
614 * hidden in the chip address.
615 */
616 if (alen > 0)
617 chip |= ((addr >> (alen * 8)) &
618 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
619#endif
620
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000621 /* Wait until bus not busy */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530622 if (wait_for_bb(i2c_base, waitdelay))
Vincent Stehlé33205e32012-12-03 05:23:16 +0000623 return 1;
Michael Jonesbb54d572011-09-04 14:01:55 -0400624
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000625 /* Start address phase - will write regoffset + len bytes data */
Tom Rini49fbf672012-02-20 18:49:16 +0000626 writew(alen + len, &i2c_base->cnt);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000627 /* Set slave address */
Michael Jonesbb54d572011-09-04 14:01:55 -0400628 writew(chip, &i2c_base->sa);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000629 /* Stop bit needed here */
Michael Jonesbb54d572011-09-04 14:01:55 -0400630 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000631 I2C_CON_STP, &i2c_base->con);
Michael Jonesbb54d572011-09-04 14:01:55 -0400632
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000633 while (alen) {
634 /* Must write reg offset (one or two bytes) */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530635 status = wait_for_event(i2c_base, waitdelay);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000636 /* Try to identify bus that is not padconf'd for I2C */
637 if (status == I2C_STAT_XRDY) {
638 i2c_error = 2;
Mugunthan V N38d943a2016-07-18 15:11:00 +0530639 printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
640 status);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000641 goto wr_exit;
642 }
Hannes Petermaierd5885052014-02-03 21:22:18 +0100643 if (status == 0 || (status & I2C_STAT_NACK)) {
Tom Rini49fbf672012-02-20 18:49:16 +0000644 i2c_error = 1;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000645 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
646 status);
647 goto wr_exit;
Tom Rini49fbf672012-02-20 18:49:16 +0000648 }
Tom Rini49fbf672012-02-20 18:49:16 +0000649 if (status & I2C_STAT_XRDY) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000650 alen--;
651 writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
652 writew(I2C_STAT_XRDY, &i2c_base->stat);
653 } else {
654 i2c_error = 1;
655 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
656 status);
657 goto wr_exit;
658 }
659 }
660 /* Address phase is over, now write data */
661 for (i = 0; i < len; i++) {
Mugunthan V N38d943a2016-07-18 15:11:00 +0530662 status = wait_for_event(i2c_base, waitdelay);
Hannes Petermaierd5885052014-02-03 21:22:18 +0100663 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000664 i2c_error = 1;
665 printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
666 status);
667 goto wr_exit;
668 }
669 if (status & I2C_STAT_XRDY) {
670 writeb(buffer[i], &i2c_base->data);
Tom Rini49fbf672012-02-20 18:49:16 +0000671 writew(I2C_STAT_XRDY, &i2c_base->stat);
672 } else {
673 i2c_error = 1;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000674 printf("i2c_write: bus not ready for data Tx (i=%d)\n",
675 i);
676 goto wr_exit;
Patil, Rachnaa9e18c22012-01-22 23:44:12 +0000677 }
678 }
Hannes Petermaierd5885052014-02-03 21:22:18 +0100679 /*
680 * poll ARDY bit for making sure that last byte really has been
681 * transferred on the bus.
682 */
683 do {
Mugunthan V N38d943a2016-07-18 15:11:00 +0530684 status = wait_for_event(i2c_base, waitdelay);
Hannes Petermaierd5885052014-02-03 21:22:18 +0100685 } while (!(status & I2C_STAT_ARDY) && timeout--);
686 if (timeout <= 0)
687 printf("i2c_write: timed out writig last byte!\n");
Patil, Rachnaa9e18c22012-01-22 23:44:12 +0000688
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000689wr_exit:
Mugunthan V N38d943a2016-07-18 15:11:00 +0530690 flush_fifo(i2c_base);
Michael Jonesbb54d572011-09-04 14:01:55 -0400691 writew(0xFFFF, &i2c_base->stat);
Tom Rini49fbf672012-02-20 18:49:16 +0000692 return i2c_error;
wdenkf8062712005-01-09 23:16:25 +0000693}
694
Mugunthan V N560037b2016-07-18 15:11:01 +0530695#ifndef CONFIG_DM_I2C
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000696/*
Mugunthan V N38d943a2016-07-18 15:11:00 +0530697 * The legacy I2C functions. These need to get removed once
698 * all users of this driver are converted to DM.
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000699 */
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200700static struct i2c *omap24_get_base(struct i2c_adapter *adap)
Dirk Behme7a8f6572009-11-02 20:36:26 +0100701{
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200702 switch (adap->hwadapnr) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000703 case 0:
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200704 return (struct i2c *)I2C_BASE1;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000705 break;
706 case 1:
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200707 return (struct i2c *)I2C_BASE2;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000708 break;
Adam Ford73010ab2017-08-11 06:39:13 -0500709#if (CONFIG_SYS_I2C_BUS_MAX > 2)
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000710 case 2:
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200711 return (struct i2c *)I2C_BASE3;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000712 break;
Adam Ford73010ab2017-08-11 06:39:13 -0500713#if (CONFIG_SYS_I2C_BUS_MAX > 3)
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000714 case 3:
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200715 return (struct i2c *)I2C_BASE4;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000716 break;
Adam Ford73010ab2017-08-11 06:39:13 -0500717#if (CONFIG_SYS_I2C_BUS_MAX > 4)
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000718 case 4:
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200719 return (struct i2c *)I2C_BASE5;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000720 break;
Koen Kooi584ff5f2012-08-08 00:57:35 +0000721#endif
Dirk Behme7a8f6572009-11-02 20:36:26 +0100722#endif
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000723#endif
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200724 default:
725 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
726 break;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000727 }
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200728 return NULL;
729}
Dirk Behme7a8f6572009-11-02 20:36:26 +0100730
Mugunthan V N38d943a2016-07-18 15:11:00 +0530731
732static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
733 int alen, uchar *buffer, int len)
734{
735 struct i2c *i2c_base = omap24_get_base(adap);
736
737 return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr,
738 alen, buffer, len);
739}
740
741
742static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
743 int alen, uchar *buffer, int len)
744{
745 struct i2c *i2c_base = omap24_get_base(adap);
746
747 return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr,
748 alen, buffer, len);
749}
750
751static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
752{
753 struct i2c *i2c_base = omap24_get_base(adap);
754 int ret;
755
756 ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay);
757 if (ret) {
758 error("%s: set i2c speed failed\n", __func__);
759 return ret;
760 }
761
762 adap->speed = speed;
763
764 return 0;
765}
766
767static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
768{
769 struct i2c *i2c_base = omap24_get_base(adap);
770
771 return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay);
772}
773
774static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
775{
776 struct i2c *i2c_base = omap24_get_base(adap);
777
778 return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip);
779}
780
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200781#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
782#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
783#endif
784#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
785#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
786#endif
Dirk Behme7a8f6572009-11-02 20:36:26 +0100787
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200788U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
Hannes Petermaierd5885052014-02-03 21:22:18 +0100789 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200790 CONFIG_SYS_OMAP24_I2C_SPEED,
791 CONFIG_SYS_OMAP24_I2C_SLAVE,
792 0)
793U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
Hannes Petermaierd5885052014-02-03 21:22:18 +0100794 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200795 CONFIG_SYS_OMAP24_I2C_SPEED1,
796 CONFIG_SYS_OMAP24_I2C_SLAVE1,
797 1)
Adam Ford73010ab2017-08-11 06:39:13 -0500798#if (CONFIG_SYS_I2C_BUS_MAX > 2)
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200799#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
800#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
801#endif
802#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
803#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
804#endif
Dirk Behme7a8f6572009-11-02 20:36:26 +0100805
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200806U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
807 omap24_i2c_read, omap24_i2c_write, NULL,
808 CONFIG_SYS_OMAP24_I2C_SPEED2,
809 CONFIG_SYS_OMAP24_I2C_SLAVE2,
810 2)
Adam Ford73010ab2017-08-11 06:39:13 -0500811#if (CONFIG_SYS_I2C_BUS_MAX > 3)
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200812#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
813#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
814#endif
815#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
816#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
817#endif
Steve Sakoman10acc712010-06-12 06:42:57 -0700818
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200819U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
820 omap24_i2c_read, omap24_i2c_write, NULL,
821 CONFIG_SYS_OMAP24_I2C_SPEED3,
822 CONFIG_SYS_OMAP24_I2C_SLAVE3,
823 3)
Adam Ford73010ab2017-08-11 06:39:13 -0500824#if (CONFIG_SYS_I2C_BUS_MAX > 4)
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200825#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
826#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
827#endif
828#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
829#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
830#endif
831
832U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
833 omap24_i2c_read, omap24_i2c_write, NULL,
834 CONFIG_SYS_OMAP24_I2C_SPEED4,
835 CONFIG_SYS_OMAP24_I2C_SLAVE4,
836 4)
837#endif
838#endif
839#endif
Mugunthan V N560037b2016-07-18 15:11:01 +0530840
841#else /* CONFIG_DM_I2C */
842
843static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
844{
845 struct omap_i2c *priv = dev_get_priv(bus);
846 int ret;
847
848 debug("i2c_xfer: %d messages\n", nmsgs);
849 for (; nmsgs > 0; nmsgs--, msg++) {
850 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
851 if (msg->flags & I2C_M_RD) {
852 ret = __omap24_i2c_read(priv->regs, priv->waitdelay,
853 msg->addr, 0, 0, msg->buf,
854 msg->len);
855 } else {
856 ret = __omap24_i2c_write(priv->regs, priv->waitdelay,
857 msg->addr, 0, 0, msg->buf,
858 msg->len);
859 }
860 if (ret) {
861 debug("i2c_write: error sending\n");
862 return -EREMOTEIO;
863 }
864 }
865
866 return 0;
867}
868
869static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
870{
871 struct omap_i2c *priv = dev_get_priv(bus);
872
873 priv->speed = speed;
874
875 return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay);
876}
877
878static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
879 uint chip_flags)
880{
881 struct omap_i2c *priv = dev_get_priv(bus);
882
883 return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr);
884}
885
886static int omap_i2c_probe(struct udevice *bus)
887{
888 struct omap_i2c *priv = dev_get_priv(bus);
889
890 __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay);
891
892 return 0;
893}
894
895static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
896{
897 struct omap_i2c *priv = dev_get_priv(bus);
898
Simon Glassba1dea42017-05-17 17:18:05 -0600899 priv->regs = map_physmem(devfdt_get_addr(bus), sizeof(void *),
Mugunthan V N560037b2016-07-18 15:11:01 +0530900 MAP_NOCACHE);
901 priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
902
903 return 0;
904}
905
906static const struct dm_i2c_ops omap_i2c_ops = {
907 .xfer = omap_i2c_xfer,
908 .probe_chip = omap_i2c_probe_chip,
909 .set_bus_speed = omap_i2c_set_bus_speed,
910};
911
912static const struct udevice_id omap_i2c_ids[] = {
Adam Ford3dc631d2017-04-17 08:09:40 -0500913 { .compatible = "ti,omap3-i2c" },
Mugunthan V N560037b2016-07-18 15:11:01 +0530914 { .compatible = "ti,omap4-i2c" },
915 { }
916};
917
918U_BOOT_DRIVER(i2c_omap) = {
919 .name = "i2c_omap",
920 .id = UCLASS_I2C,
921 .of_match = omap_i2c_ids,
922 .ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
923 .probe = omap_i2c_probe,
924 .priv_auto_alloc_size = sizeof(struct omap_i2c),
925 .ops = &omap_i2c_ops,
926 .flags = DM_FLAG_PRE_RELOC,
927};
928
929#endif /* CONFIG_DM_I2C */