blob: 88f80b05a90268e232beb33a43028c848962a24c [file] [log] [blame]
Kever Yang34ead0f2019-07-09 22:05:55 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <debug_uart.h>
8#include <dm.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Kever Yang34ead0f2019-07-09 22:05:55 +080012#include <ram.h>
13#include <spl.h>
14#include <version.h>
15#include <asm/io.h>
16#include <asm/arch-rockchip/bootrom.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060017#include <linux/bitops.h>
Kever Yang34ead0f2019-07-09 22:05:55 +080018
19#define TIMER_LOAD_COUNT_L 0x00
20#define TIMER_LOAD_COUNT_H 0x04
21#define TIMER_CONTROL_REG 0x10
22#define TIMER_EN 0x1
23#define TIMER_FMODE BIT(0)
24#define TIMER_RMODE BIT(1)
25
26__weak void rockchip_stimer_init(void)
27{
28 /* If Timer already enabled, don't re-init it */
29 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
30
31 if (reg & TIMER_EN)
32 return;
33
34#ifndef CONFIG_ARM64
35 asm volatile("mcr p15, 0, %0, c14, c0, 0"
36 : : "r"(COUNTER_FREQUENCY));
37#endif
38
39 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
40 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
41 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
42 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
43 TIMER_CONTROL_REG);
44}
45
Suniel Maheshfe65e712020-02-03 19:20:05 +053046__weak int board_early_init_f(void)
47{
48 return 0;
49}
50
Kever Yang34ead0f2019-07-09 22:05:55 +080051void board_init_f(ulong dummy)
52{
53 struct udevice *dev;
54 int ret;
55
Suniel Maheshfe65e712020-02-03 19:20:05 +053056 board_early_init_f();
57
Chris Webba88cbf92019-07-19 14:23:11 +010058#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
Kever Yang34ead0f2019-07-09 22:05:55 +080059 /*
60 * Debug UART can be used from here if required:
61 *
62 * debug_uart_init();
63 * printch('a');
64 * printhex8(0x1234);
65 * printascii("string");
66 */
67 debug_uart_init();
Chris Webb45dd8012019-07-19 14:23:55 +010068#ifdef CONFIG_TPL_BANNER_PRINT
Kever Yang34ead0f2019-07-09 22:05:55 +080069 printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
70 U_BOOT_TIME ")\n");
71#endif
Chris Webb45dd8012019-07-19 14:23:55 +010072#endif
Kever Yang34ead0f2019-07-09 22:05:55 +080073 ret = spl_early_init();
74 if (ret) {
75 debug("spl_early_init() failed: %d\n", ret);
76 hang();
77 }
78
79 /* Init secure timer */
80 rockchip_stimer_init();
81 /* Init ARM arch timer in arch/arm/cpu/ */
82 timer_init();
83
84 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
85 if (ret) {
86 printf("DRAM init failed: %d\n", ret);
87 return;
88 }
89}
90
Peng Fanaa050c52019-08-07 06:40:53 +000091int board_return_to_bootrom(struct spl_image_info *spl_image,
92 struct spl_boot_device *bootdev)
Kever Yang34ead0f2019-07-09 22:05:55 +080093{
94 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
Peng Fanaa050c52019-08-07 06:40:53 +000095
96 return 0;
Kever Yang34ead0f2019-07-09 22:05:55 +080097}
98
99u32 spl_boot_device(void)
100{
101 return BOOT_DEVICE_BOOTROM;
102}