blob: 74f185c87f48a202035b2eee32296e2ed53e84a6 [file] [log] [blame]
Kever Yang34ead0f2019-07-09 22:05:55 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <debug_uart.h>
8#include <dm.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Kever Yang34ead0f2019-07-09 22:05:55 +080012#include <ram.h>
13#include <spl.h>
14#include <version.h>
15#include <asm/io.h>
16#include <asm/arch-rockchip/bootrom.h>
17
18#define TIMER_LOAD_COUNT_L 0x00
19#define TIMER_LOAD_COUNT_H 0x04
20#define TIMER_CONTROL_REG 0x10
21#define TIMER_EN 0x1
22#define TIMER_FMODE BIT(0)
23#define TIMER_RMODE BIT(1)
24
25__weak void rockchip_stimer_init(void)
26{
27 /* If Timer already enabled, don't re-init it */
28 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
29
30 if (reg & TIMER_EN)
31 return;
32
33#ifndef CONFIG_ARM64
34 asm volatile("mcr p15, 0, %0, c14, c0, 0"
35 : : "r"(COUNTER_FREQUENCY));
36#endif
37
38 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
39 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
40 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
41 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
42 TIMER_CONTROL_REG);
43}
44
Suniel Maheshfe65e712020-02-03 19:20:05 +053045__weak int board_early_init_f(void)
46{
47 return 0;
48}
49
Kever Yang34ead0f2019-07-09 22:05:55 +080050void board_init_f(ulong dummy)
51{
52 struct udevice *dev;
53 int ret;
54
Suniel Maheshfe65e712020-02-03 19:20:05 +053055 board_early_init_f();
56
Chris Webba88cbf92019-07-19 14:23:11 +010057#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
Kever Yang34ead0f2019-07-09 22:05:55 +080058 /*
59 * Debug UART can be used from here if required:
60 *
61 * debug_uart_init();
62 * printch('a');
63 * printhex8(0x1234);
64 * printascii("string");
65 */
66 debug_uart_init();
Chris Webb45dd8012019-07-19 14:23:55 +010067#ifdef CONFIG_TPL_BANNER_PRINT
Kever Yang34ead0f2019-07-09 22:05:55 +080068 printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
69 U_BOOT_TIME ")\n");
70#endif
Chris Webb45dd8012019-07-19 14:23:55 +010071#endif
Kever Yang34ead0f2019-07-09 22:05:55 +080072 ret = spl_early_init();
73 if (ret) {
74 debug("spl_early_init() failed: %d\n", ret);
75 hang();
76 }
77
78 /* Init secure timer */
79 rockchip_stimer_init();
80 /* Init ARM arch timer in arch/arm/cpu/ */
81 timer_init();
82
83 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
84 if (ret) {
85 printf("DRAM init failed: %d\n", ret);
86 return;
87 }
88}
89
Peng Fanaa050c52019-08-07 06:40:53 +000090int board_return_to_bootrom(struct spl_image_info *spl_image,
91 struct spl_boot_device *bootdev)
Kever Yang34ead0f2019-07-09 22:05:55 +080092{
93 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
Peng Fanaa050c52019-08-07 06:40:53 +000094
95 return 0;
Kever Yang34ead0f2019-07-09 22:05:55 +080096}
97
98u32 spl_boot_device(void)
99{
100 return BOOT_DEVICE_BOOTROM;
101}