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git01.mediatek.com / filogic / uboot / d26a1068a0a4a0095bf4d8fec86f325e77ef3a63 / . / drivers / block / sata_sil.h
blob: 9f3a37f508f6618e548d97e6fbab5d1b298350c5 [file] [log] [blame]
Tang Yuantian4511ccc2011-10-07 19:26:58 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Author: Tang Yuantian <b29983@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef SATA_SIL3132_H
22#define SATA_SIL3132_H
23
24#define READ_CMD 0
25#define WRITE_CMD 1
26
Tang Yuantian4511ccc2011-10-07 19:26:58 +0000[diff] [blame]27/*
28 * SATA device driver struct for each dev
29 */
30struct sil_sata {
31 char name[12];
32 void *port; /* the port base address */
33 int lba48;
34 u16 pio;
35 u16 mwdma;
36 u16 udma;
37 pci_dev_t devno;
38 int wcache;
39 int flush;
40 int flush_ext;
41};
42
43/* sata info for each controller */
44struct sata_info {
45 ulong iobase[3];
46 pci_dev_t devno;
47 int portbase;
48 int maxport;
49};
50
51/*
52 * Scatter gather entry (SGE),MUST 8 bytes aligned
53 */
54struct sil_sge {
55 __le64 addr;
56 __le32 cnt;
57 __le32 flags;
58} __attribute__ ((aligned(8), packed));
59
60/*
61 * Port request block, MUST 8 bytes aligned
62 */
63struct sil_prb {
64 __le16 ctrl;
65 __le16 prot;
66 __le32 rx_cnt;
67 struct sata_fis_h2d fis;
68} __attribute__ ((aligned(8), packed));
69
70struct sil_cmd_block {
71 struct sil_prb prb;
72 struct sil_sge sge;
73};
74
75enum {
76 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
77 HOST_CTRL = 0x40,
78 HOST_IRQ_STAT = 0x44,
79 HOST_PHY_CFG = 0x48,
80 HOST_BIST_CTRL = 0x50,
81 HOST_BIST_PTRN = 0x54,
82 HOST_BIST_STAT = 0x58,
83 HOST_MEM_BIST_STAT = 0x5c,
84 HOST_FLASH_CMD = 0x70,
85 /* 8 bit regs */
86 HOST_FLASH_DATA = 0x74,
87 HOST_TRANSITION_DETECT = 0x75,
88 HOST_GPIO_CTRL = 0x76,
89 HOST_I2C_ADDR = 0x78, /* 32 bit */
90 HOST_I2C_DATA = 0x7c,
91 HOST_I2C_XFER_CNT = 0x7e,
92 HOST_I2C_CTRL = 0x7f,
93
94 /* HOST_SLOT_STAT bits */
95 HOST_SSTAT_ATTN = (1 << 31),
96
97 /* HOST_CTRL bits */
98 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
99 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
100 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
101 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
102 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
103 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
104
105 /*
106 * Port registers
107 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
108 */
109 PORT_REGS_SIZE = 0x2000,
110
111 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
112 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
113
114 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
115 PORT_PMP_STATUS = 0x0000, /* port device status offset */
116 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
117 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
118
119 /* 32 bit regs */
120 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
121 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
122 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
123 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
124 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
125 PORT_ACTIVATE_UPPER_ADDR = 0x101c,
126 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
127 PORT_CMD_ERR = 0x1024, /* command error number */
128 PORT_FIS_CFG = 0x1028,
129 PORT_FIFO_THRES = 0x102c,
130
131 /* 16 bit regs */
132 PORT_DECODE_ERR_CNT = 0x1040,
133 PORT_DECODE_ERR_THRESH = 0x1042,
134 PORT_CRC_ERR_CNT = 0x1044,
135 PORT_CRC_ERR_THRESH = 0x1046,
136 PORT_HSHK_ERR_CNT = 0x1048,
137 PORT_HSHK_ERR_THRESH = 0x104a,
138
139 /* 32 bit regs */
140 PORT_PHY_CFG = 0x1050,
141 PORT_SLOT_STAT = 0x1800,
142 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 */
143 PORT_CONTEXT = 0x1e04,
144 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 */
145 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 */
146 PORT_SCONTROL = 0x1f00,
147 PORT_SSTATUS = 0x1f04,
148 PORT_SERROR = 0x1f08,
149 PORT_SACTIVE = 0x1f0c,
150
151 /* PORT_CTRL_STAT bits */
152 PORT_CS_PORT_RST = (1 << 0), /* port reset */
153 PORT_CS_DEV_RST = (1 << 1), /* device reset */
154 PORT_CS_INIT = (1 << 2), /* port initialize */
155 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
156 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
157 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
158 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
159 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
160 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
161
162 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
163 /* bits[11:0] are masked */
164 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
165 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
166 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
167 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
168 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
169 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
170 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
171 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
172 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
173 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
174 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
175 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
176
177 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
178 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
179 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
180
181 /* bits[27:16] are unmasked (raw) */
182 PORT_IRQ_RAW_SHIFT = 16,
183 PORT_IRQ_MASKED_MASK = 0x7ff,
184 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
185
186 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
187 PORT_IRQ_STEER_SHIFT = 30,
188 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
189
190 /* PORT_CMD_ERR constants */
191 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
192 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
193 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
194 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
195 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
196 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
197 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
198 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
199
200 /* bits of PRB control field */
201 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
202 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
203 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
204 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
205 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
206
207 /* PRB protocol field */
208 PRB_PROT_PACKET = (1 << 0),
209 PRB_PROT_TCQ = (1 << 1),
210 PRB_PROT_NCQ = (1 << 2),
211 PRB_PROT_READ = (1 << 3),
212 PRB_PROT_WRITE = (1 << 4),
213 PRB_PROT_TRANSPARENT = (1 << 5),
214
215 /*
216 * Other constants
217 */
218 SGE_TRM = (1 << 31), /* Last SGE in chain */
219 SGE_LNK = (1 << 30), /* linked list
220 Points to SGT, not SGE */
221 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
222 data address ignored */
223
224 CMD_ERR = 0x21,
225};
226
227#endif