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wdenk21136db2003-07-16 21:53:01 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenk21136db2003-07-16 21:53:01 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
wdenkbe9c1cb2004-02-24 02:00:03 +000032#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenk21136db2003-07-16 21:53:01 +000033#define CONFIG_ICECUBE 1 /* ... on IceCube board */
34
wdenk236d3fc2003-12-20 22:45:10 +000035#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenk21136db2003-07-16 21:53:01 +000036
37#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38#define BOOTFLAG_WARM 0x02 /* Software reboot */
39
wdenk02379022003-08-05 18:22:44 +000040#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
wdenk21136db2003-07-16 21:53:01 +000041#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
42# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
43#endif
44
45/*
46 * Serial console configuration
47 */
48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51
wdenk02379022003-08-05 18:22:44 +000052
53#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
54/*
55 * PCI Mapping:
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
58 */
Rafal Jaworowski0b892e82006-03-29 13:17:09 +020059#define CONFIG_PCI
60
61#if defined(CONFIG_PCI)
wdenk02379022003-08-05 18:22:44 +000062#define CONFIG_PCI_PNP 1
63#define CONFIG_PCI_SCAN_SHOW 1
64
65#define CONFIG_PCI_MEM_BUS 0x40000000
66#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
67#define CONFIG_PCI_MEM_SIZE 0x10000000
68
69#define CONFIG_PCI_IO_BUS 0x50000000
70#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
71#define CONFIG_PCI_IO_SIZE 0x01000000
Rafal Jaworowski0b892e82006-03-29 13:17:09 +020072#define ADD_PCI_CMD CFG_CMD_PCI
73#endif
wdenk02379022003-08-05 18:22:44 +000074
wdenk391b5742004-10-10 23:27:33 +000075#define CFG_XLB_PIPELINING 1
76
wdenk02379022003-08-05 18:22:44 +000077#define CONFIG_NET_MULTI 1
Marian Balakowiczaab8c492005-10-28 22:30:33 +020078#define CONFIG_MII 1
wdenk02379022003-08-05 18:22:44 +000079#define CONFIG_EEPRO100 1
80#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkf6a6ac12003-09-17 15:10:32 +000081#define CONFIG_NS8382X 1
wdenk02379022003-08-05 18:22:44 +000082
wdenk02379022003-08-05 18:22:44 +000083#else /* MPC5100 */
84
Marian Balakowiczaab8c492005-10-28 22:30:33 +020085#define CONFIG_MII 1
wdenk02379022003-08-05 18:22:44 +000086#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
87
88#endif
89
wdenk6ea1cf02004-02-27 08:20:54 +000090/* Partitions */
91#define CONFIG_MAC_PARTITION
92#define CONFIG_DOS_PARTITION
wdenke2d6d742004-09-28 20:34:50 +000093#define CONFIG_ISO_PARTITION
wdenk6ea1cf02004-02-27 08:20:54 +000094
wdenk5f495752004-02-26 23:46:20 +000095/* USB */
96#if 1
Markus Klotzbuecherd209de62006-11-27 11:46:46 +010097#define CONFIG_USB_OHCI_NEW
wdenk5f495752004-02-26 23:46:20 +000098#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
wdenk5f495752004-02-26 23:46:20 +000099#define CONFIG_USB_STORAGE
Markus Klotzbuecherd209de62006-11-27 11:46:46 +0100100
101#undef CFG_USB_OHCI_BOARD_INIT
102#define CFG_USB_OHCI_CPU_INIT
103#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB
104#define CFG_USB_OHCI_SLOT_NAME "mpc5200"
105#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
106
wdenk5f495752004-02-26 23:46:20 +0000107#else
108#define ADD_USB_CMD 0
109#endif
110
wdenk8d5d28a2005-04-02 22:37:54 +0000111#define CONFIG_TIMESTAMP /* Print image info with timestamp */
112
wdenk21136db2003-07-16 21:53:01 +0000113/*
114 * Supported commands
115 */
wdenk8d5d28a2005-04-02 22:37:54 +0000116#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
117 CFG_CMD_EEPROM | \
118 CFG_CMD_FAT | \
119 CFG_CMD_I2C | \
120 CFG_CMD_IDE | \
121 CFG_CMD_NFS | \
122 CFG_CMD_SNTP | \
123 ADD_PCI_CMD | \
124 ADD_USB_CMD )
wdenk21136db2003-07-16 21:53:01 +0000125
126/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
127#include <cmd_confdefs.h>
128
wdenk4b16c2e2003-11-07 13:42:26 +0000129#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
130# define CFG_LOWBOOT 1
131# define CFG_LOWBOOT16 1
132#endif
133#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100134#if defined(CONFIG_LITE5200B)
135# error CFG_LOWBOOT08 is incompatible with the Lite5200B
136#else
wdenk4b16c2e2003-11-07 13:42:26 +0000137# define CFG_LOWBOOT 1
138# define CFG_LOWBOOT08 1
139#endif
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100140#endif
wdenk4b16c2e2003-11-07 13:42:26 +0000141
wdenk21136db2003-07-16 21:53:01 +0000142/*
143 * Autobooting
144 */
145#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk4b16c2e2003-11-07 13:42:26 +0000146
147#define CONFIG_PREBOOT "echo;" \
148 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
149 "echo"
150
151#undef CONFIG_BOOTARGS
152
153#define CONFIG_EXTRA_ENV_SETTINGS \
154 "netdev=eth0\0" \
155 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100156 "nfsroot=${serverip}:${rootpath}\0" \
wdenk4b16c2e2003-11-07 13:42:26 +0000157 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100158 "addip=setenv bootargs ${bootargs} " \
159 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
160 ":${hostname}:${netdev}:off panic=1\0" \
wdenk4b16c2e2003-11-07 13:42:26 +0000161 "flash_nfs=run nfsargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100162 "bootm ${kernel_addr}\0" \
wdenk4b16c2e2003-11-07 13:42:26 +0000163 "flash_self=run ramargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100164 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
165 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk4b16c2e2003-11-07 13:42:26 +0000166 "rootpath=/opt/eldk/ppc_82xx\0" \
167 "bootfile=/tftpboot/MPC5200/uImage\0" \
168 ""
169
170#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk21136db2003-07-16 21:53:01 +0000171
wdenk6e2bf7a2003-09-16 11:39:10 +0000172#if defined(CONFIG_MPC5200)
173/*
174 * IPB Bus clocking configuration.
175 */
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100176#if defined(CONFIG_LITE5200B)
177#define CFG_IPBSPEED_133 /* define for 133MHz speed */
178#else
179#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
wdenk6e2bf7a2003-09-16 11:39:10 +0000180#endif
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100181#endif /* CONFIG_MPC5200 */
wdenk21136db2003-07-16 21:53:01 +0000182/*
183 * I2C configuration
184 */
wdenk25521902003-09-13 19:01:12 +0000185#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
dzu62177922003-09-30 14:08:43 +0000186#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
187
188#define CFG_I2C_SPEED 100000 /* 100 kHz */
wdenk25521902003-09-13 19:01:12 +0000189#define CFG_I2C_SLAVE 0x7F
190
191/*
192 * EEPROM configuration
193 */
194#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
195#define CFG_I2C_EEPROM_ADDR_LEN 1
196#define CFG_EEPROM_PAGE_WRITE_BITS 3
dzu62177922003-09-30 14:08:43 +0000197#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenk21136db2003-07-16 21:53:01 +0000198
199/*
200 * Flash configuration
201 */
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100202#if defined(CONFIG_LITE5200B)
203#define CFG_FLASH_BASE 0xFE000000
204#define CFG_FLASH_SIZE 0x01000000
205#if !defined(CFG_LOWBOOT)
206#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000)
207#else /* CFG_LOWBOOT */
208#if defined(CFG_LOWBOOT08)
209# error CFG_LOWBOOT08 is incompatible with the Lite5200B
210#endif
211#if defined(CFG_LOWBOOT16)
212#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000)
213#endif
214#endif /* CFG_LOWBOOT */
215#else /* !CONFIG_LITE5200B (IceCube)*/
wdenke55402c2004-03-14 16:51:43 +0000216#define CFG_FLASH_BASE 0xFF000000
wdenkeb20ad32003-09-05 23:19:14 +0000217#define CFG_FLASH_SIZE 0x01000000
wdenk4b16c2e2003-11-07 13:42:26 +0000218#if !defined(CFG_LOWBOOT)
wdenke55402c2004-03-14 16:51:43 +0000219#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
wdenk4b16c2e2003-11-07 13:42:26 +0000220#else /* CFG_LOWBOOT */
221#if defined(CFG_LOWBOOT08)
wdenke55402c2004-03-14 16:51:43 +0000222#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000)
wdenkeb20ad32003-09-05 23:19:14 +0000223#endif
wdenk4b16c2e2003-11-07 13:42:26 +0000224#if defined(CFG_LOWBOOT16)
wdenke55402c2004-03-14 16:51:43 +0000225#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
wdenk4b16c2e2003-11-07 13:42:26 +0000226#endif
227#endif /* CFG_LOWBOOT */
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100228#endif /* CONFIG_LITE5200B */
wdenk4b16c2e2003-11-07 13:42:26 +0000229#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
wdenkeb20ad32003-09-05 23:19:14 +0000230
wdenk21136db2003-07-16 21:53:01 +0000231#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
232
233#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
234#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
235
wdenk02379022003-08-05 18:22:44 +0000236#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
wdenk21136db2003-07-16 21:53:01 +0000237
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100238#if defined(CONFIG_LITE5200B)
239#define CFG_FLASH_CFI_DRIVER
240#define CFG_FLASH_CFI
241#define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START}
242#endif
243
wdenk21136db2003-07-16 21:53:01 +0000244
245/*
246 * Environment settings
247 */
wdenk02379022003-08-05 18:22:44 +0000248#define CFG_ENV_IS_IN_FLASH 1
wdenk21136db2003-07-16 21:53:01 +0000249#define CFG_ENV_SIZE 0x10000
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100250#if defined(CONFIG_LITE5200B)
251#define CFG_ENV_SECT_SIZE 0x20000
252#else
wdenk02379022003-08-05 18:22:44 +0000253#define CFG_ENV_SECT_SIZE 0x10000
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100254#endif
wdenk02379022003-08-05 18:22:44 +0000255#define CONFIG_ENV_OVERWRITE 1
wdenk21136db2003-07-16 21:53:01 +0000256
257/*
258 * Memory map
259 */
wdenke55402c2004-03-14 16:51:43 +0000260#define CFG_MBAR 0xF0000000
wdenk21136db2003-07-16 21:53:01 +0000261#define CFG_SDRAM_BASE 0x00000000
wdenk5d841732003-08-17 18:55:18 +0000262#define CFG_DEFAULT_MBAR 0x80000000
wdenk21136db2003-07-16 21:53:01 +0000263
264/* Use SRAM until RAM will be available */
265#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
266#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
267
268
269#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
270#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
271#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
272
273#define CFG_MONITOR_BASE TEXT_BASE
274#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
wdenk02379022003-08-05 18:22:44 +0000275# define CFG_RAMBOOT 1
wdenk21136db2003-07-16 21:53:01 +0000276#endif
277
wdenk78ae91f2003-12-03 23:53:42 +0000278#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk21136db2003-07-16 21:53:01 +0000279#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
280#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
281
282/*
283 * Ethernet configuration
284 */
wdenkbe9c1cb2004-02-24 02:00:03 +0000285#define CONFIG_MPC5xxx_FEC 1
wdenk3902d702004-04-15 18:22:41 +0000286/*
wdenka09491a2004-04-08 22:31:29 +0000287 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
288 */
289/* #define CONFIG_FEC_10MBIT 1 */
wdenk1ebf41e2004-01-02 14:00:00 +0000290#define CONFIG_PHY_ADDR 0x00
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100291#if defined(CONFIG_LITE5200B)
292#define CONFIG_FEC_MII100 1
293#endif
wdenk21136db2003-07-16 21:53:01 +0000294
295/*
296 * GPIO configuration
297 */
wdenk236d3fc2003-12-20 22:45:10 +0000298#ifdef CONFIG_MPC5200_DDR
299#define CFG_GPS_PORT_CONFIG 0x90000004
300#else
wdenk6f5ee102003-09-18 20:10:12 +0000301#define CFG_GPS_PORT_CONFIG 0x10000004
wdenk236d3fc2003-12-20 22:45:10 +0000302#endif
wdenk21136db2003-07-16 21:53:01 +0000303
304/*
305 * Miscellaneous configurable options
306 */
307#define CFG_LONGHELP /* undef to save memory */
308#define CFG_PROMPT "=> " /* Monitor Command Prompt */
309#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
310#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
311#else
312#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
313#endif
314#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
315#define CFG_MAXARGS 16 /* max number of command args */
316#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
317
318#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
319#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
320
321#define CFG_LOAD_ADDR 0x100000 /* default load address */
322
323#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
324
325/*
326 * Various low-level settings
327 */
wdenk655a0f92003-10-30 21:49:38 +0000328#if defined(CONFIG_MPC5200)
wdenk4cc02a82003-09-11 23:06:34 +0000329#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
330#define CFG_HID0_FINAL HID0_ICE
wdenk655a0f92003-10-30 21:49:38 +0000331#else
332#define CFG_HID0_INIT 0
333#define CFG_HID0_FINAL 0
334#endif
wdenk21136db2003-07-16 21:53:01 +0000335
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100336#if defined(CONFIG_LITE5200B)
337#define CFG_CS1_START CFG_FLASH_BASE
338#define CFG_CS1_SIZE CFG_FLASH_SIZE
339#define CFG_CS1_CFG 0x00047800
340#define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE)
341#define CFG_CS0_SIZE CFG_FLASH_SIZE
342#define CFG_BOOTCS_START CFG_CS0_START
343#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
344#define CFG_BOOTCS_CFG 0x00047800
345#else /* IceCube aka Lite5200 */
wdenk236d3fc2003-12-20 22:45:10 +0000346#ifdef CONFIG_MPC5200_DDR
347
wdenka09491a2004-04-08 22:31:29 +0000348#define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE)
wdenk236d3fc2003-12-20 22:45:10 +0000349#define CFG_BOOTCS_SIZE 0x00800000
350#define CFG_BOOTCS_CFG 0x00047801
wdenka09491a2004-04-08 22:31:29 +0000351#define CFG_CS1_START CFG_FLASH_BASE
wdenk236d3fc2003-12-20 22:45:10 +0000352#define CFG_CS1_SIZE 0x00800000
353#define CFG_CS1_CFG 0x00047800
354
355#else /* !CONFIG_MPC5200_DDR */
356
wdenk21136db2003-07-16 21:53:01 +0000357#define CFG_BOOTCS_START CFG_FLASH_BASE
358#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
359#define CFG_BOOTCS_CFG 0x00047801
360#define CFG_CS0_START CFG_FLASH_BASE
361#define CFG_CS0_SIZE CFG_FLASH_SIZE
362
wdenk236d3fc2003-12-20 22:45:10 +0000363#endif /* CONFIG_MPC5200_DDR */
Wolfgang Denk315b46a2006-03-17 11:42:53 +0100364#endif /*CONFIG_LITE5200B */
wdenk236d3fc2003-12-20 22:45:10 +0000365
wdenk21136db2003-07-16 21:53:01 +0000366#define CFG_CS_BURST 0x00000000
367#define CFG_CS_DEADCYCLE 0x33333333
368
369#define CFG_RESET_ADDRESS 0xff000000
370
wdenk6ea1cf02004-02-27 08:20:54 +0000371/*-----------------------------------------------------------------------
wdenkacd9b102004-03-14 00:59:59 +0000372 * USB stuff
373 *-----------------------------------------------------------------------
374 */
wdenk369d43d2004-03-14 14:09:05 +0000375#define CONFIG_USB_CLOCK 0x0001BBBB
376#define CONFIG_USB_CONFIG 0x00001000
wdenkacd9b102004-03-14 00:59:59 +0000377
378/*-----------------------------------------------------------------------
wdenk6ea1cf02004-02-27 08:20:54 +0000379 * IDE/ATA stuff Supports IDE harddisk
380 *-----------------------------------------------------------------------
381 */
382
383#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
384
385#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
386#undef CONFIG_IDE_LED /* LED for ide not supported */
387
388#define CONFIG_IDE_RESET /* reset for ide supported */
389#define CONFIG_IDE_PREINIT
390
391#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
wdenke2d6d742004-09-28 20:34:50 +0000392#define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
wdenk6ea1cf02004-02-27 08:20:54 +0000393
394#define CFG_ATA_IDE0_OFFSET 0x0000
395
396#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
397
398/* Offset for data I/O */
399#define CFG_ATA_DATA_OFFSET (0x0060)
400
401/* Offset for normal register accesses */
402#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
403
404/* Offset for alternate registers */
wdenke55402c2004-03-14 16:51:43 +0000405#define CFG_ATA_ALT_OFFSET (0x005C)
wdenk6ea1cf02004-02-27 08:20:54 +0000406
407/* Interval between registers */
408#define CFG_ATA_STRIDE 4
409
wdenke2d6d742004-09-28 20:34:50 +0000410#define CONFIG_ATAPI 1
411
wdenk21136db2003-07-16 21:53:01 +0000412#endif /* __CONFIG_H */