| Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ARCH_QEMU_H_ |
| 8 | #define _ARCH_QEMU_H_ |
| 9 | |
| Bin Meng | a8b70a1 | 2015-05-24 00:12:33 +0800 | [diff] [blame] | 10 | /* Programmable Attribute Map (PAM) Registers */ |
| 11 | #define I440FX_PAM 0x59 |
| 12 | #define Q35_PAM 0x90 |
| 13 | #define PAM_NUM 7 |
| 14 | #define PAM_RW 0x33 |
| 15 | |
| Bin Meng | 8f71dc8 | 2015-07-22 01:21:11 -0700 | [diff] [blame] | 16 | /* X-Bus Chip Select Register */ |
| 17 | #define XBCS 0x4e |
| 18 | #define APIC_EN (1 << 8) |
| 19 | |
| Bin Meng | 19c7739 | 2015-05-25 22:36:26 +0800 | [diff] [blame] | 20 | /* IDE Timing Register */ |
| 21 | #define IDE0_TIM 0x40 |
| 22 | #define IDE1_TIM 0x42 |
| Bin Meng | 8f71dc8 | 2015-07-22 01:21:11 -0700 | [diff] [blame] | 23 | #define IDE_DECODE_EN (1 << 15) |
| Bin Meng | 19c7739 | 2015-05-25 22:36:26 +0800 | [diff] [blame] | 24 | |
| Bin Meng | 33e140d | 2015-07-22 01:21:14 -0700 | [diff] [blame] | 25 | /* PCIe ECAM Base Address Register */ |
| 26 | #define PCIEX_BAR 0x60 |
| 27 | #define BAR_EN (1 << 0) |
| 28 | |
| Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 29 | /* I/O Ports */ |
| 30 | #define CMOS_ADDR_PORT 0x70 |
| 31 | #define CMOS_DATA_PORT 0x71 |
| 32 | |
| 33 | #define LOW_RAM_ADDR 0x34 |
| 34 | #define HIGH_RAM_ADDR 0x35 |
| 35 | |
| Miao Yan | 35603ff | 2016-01-20 01:57:05 -0800 | [diff] [blame] | 36 | /* PM registers */ |
| 37 | #define PMBA 0x40 |
| 38 | #define PMREGMISC 0x80 |
| 39 | #define PMIOSE (1 << 0) |
| 40 | |
| Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 41 | #endif /* _ARCH_QEMU_H_ */ |