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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hueee86ff2015-10-26 19:47:52 +08002/*
3 * Copyright (C) 2015 Freescale Semiconductor
Yangbo Lubb32e682021-06-03 10:51:19 +08004 * Copyright 2019-2021 NXP
Mingkai Hueee86ff2015-10-26 19:47:52 +08005 */
6
7#ifndef __LS1043A_COMMON_H
8#define __LS1043A_COMMON_H
9
Sumit Garg2a2857b2017-03-30 09:52:38 +053010/* SPL build */
11#ifdef CONFIG_SPL_BUILD
12#define SPL_NO_FMAN
13#define SPL_NO_DSPI
14#define SPL_NO_PCIE
15#define SPL_NO_ENV
16#define SPL_NO_MISC
17#define SPL_NO_USB
18#define SPL_NO_SATA
19#define SPL_NO_QE
20#define SPL_NO_EEPROM
21#endif
22#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
23#define SPL_NO_MMC
24#endif
Yangbo Lu83c4ece2017-09-15 09:51:58 +080025#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
Sumit Garg2a2857b2017-03-30 09:52:38 +053026#define SPL_NO_IFC
27#endif
28
Bharat Bhushan882b6322017-03-22 12:06:27 +053029#include <asm/arch/stream_id_lsch2.h>
Mingkai Hueee86ff2015-10-26 19:47:52 +080030#include <asm/arch/config.h>
Mingkai Hueee86ff2015-10-26 19:47:52 +080031
32/* Link Definitions */
Mingkai Hueee86ff2015-10-26 19:47:52 +080033
Mingkai Hueee86ff2015-10-26 19:47:52 +080034#define CONFIG_VERY_BIG_RAM
35#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
36#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
37#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shaohui Xief6c83952015-11-23 15:23:48 +080038#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
Mingkai Hueee86ff2015-10-26 19:47:52 +080039
Michael Wallef056e0f2020-06-01 21:53:26 +020040#define CPU_RELEASE_ADDR secondary_boot_addr
Hou Zhiqiangc7098fa2015-10-26 19:47:57 +080041
Mingkai Hueee86ff2015-10-26 19:47:52 +080042/* Serial Port */
Mingkai Hueee86ff2015-10-26 19:47:52 +080043#define CONFIG_SYS_NS16550_SERIAL
44#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +080045#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Hueee86ff2015-10-26 19:47:52 +080046
Gong Qianyuf671f6c2015-10-26 19:47:56 +080047/* SD boot SPL */
48#ifdef CONFIG_SD_BOOT
Udit Agarwal22ec2382019-11-07 16:11:32 +000049#ifdef CONFIG_NXP_ESBC
Ruchika Guptad6b89202017-04-17 18:07:17 +053050#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
51/*
52 * HDR would be appended at end of image and copied to DDR along
53 * with U-Boot image. Here u-boot max. size is 512K. So if binary
54 * size increases then increase this size in case of secure boot as
55 * it uses raw u-boot image instead of fit image.
56 */
57#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
58#else
59#define CONFIG_SYS_MONITOR_LEN 0x100000
Udit Agarwal22ec2382019-11-07 16:11:32 +000060#endif /* ifdef CONFIG_NXP_ESBC */
Gong Qianyuf671f6c2015-10-26 19:47:56 +080061#endif
62
Gong Qianyu8168a0f2015-10-26 19:47:53 +080063/* NAND SPL */
64#ifdef CONFIG_NAND_BOOT
Gong Qianyu8168a0f2015-10-26 19:47:53 +080065#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
66#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
Ruchika Guptaba688752017-04-17 18:07:18 +053067
Udit Agarwal22ec2382019-11-07 16:11:32 +000068#ifdef CONFIG_NXP_ESBC
Ruchika Guptaba688752017-04-17 18:07:18 +053069#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Udit Agarwal22ec2382019-11-07 16:11:32 +000070#endif /* ifdef CONFIG_NXP_ESBC */
Ruchika Guptaba688752017-04-17 18:07:18 +053071
72#ifdef CONFIG_U_BOOT_HDR_SIZE
73/*
74 * HDR would be appended at end of image and copied to DDR along
75 * with U-Boot image. Here u-boot max. size is 512K. So if binary
76 * size increases then increase this size in case of secure boot as
77 * it uses raw u-boot image instead of fit image.
78 */
79#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
80#else
81#define CONFIG_SYS_MONITOR_LEN 0x100000
82#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
83
Gong Qianyu8168a0f2015-10-26 19:47:53 +080084#endif
85
Biwen Li46de4002021-02-05 19:01:56 +080086/* GPIO */
Biwen Li46de4002021-02-05 19:01:56 +080087
Mingkai Hueee86ff2015-10-26 19:47:52 +080088/* IFC */
Sumit Garg2a2857b2017-03-30 09:52:38 +053089#ifndef SPL_NO_IFC
Rajesh Bhagatb89aed42018-11-05 18:02:44 +000090#if defined(CONFIG_TFABOOT) || \
91 (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
Mingkai Hueee86ff2015-10-26 19:47:52 +080092/*
93 * CONFIG_SYS_FLASH_BASE has the final address (core view)
94 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
95 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
96 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
97 */
98#define CONFIG_SYS_FLASH_BASE 0x60000000
99#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
100#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
101
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900102#ifdef CONFIG_MTD_NOR_FLASH
Mingkai Hueee86ff2015-10-26 19:47:52 +0800103#define CONFIG_SYS_FLASH_QUIET_TEST
104#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
105#endif
Gong Qianyu760df892016-01-25 15:16:06 +0800106#endif
Sumit Garg2a2857b2017-03-30 09:52:38 +0530107#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +0800108
109/* I2C */
Mingkai Hueee86ff2015-10-26 19:47:52 +0800110
111/* PCIe */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530112#ifndef SPL_NO_PCIE
Mingkai Hueee86ff2015-10-26 19:47:52 +0800113#define CONFIG_PCIE1 /* PCIE controller 1 */
114#define CONFIG_PCIE2 /* PCIE controller 2 */
115#define CONFIG_PCIE3 /* PCIE controller 3 */
Mingkai Hueee86ff2015-10-26 19:47:52 +0800116
Mingkai Hueee86ff2015-10-26 19:47:52 +0800117#ifdef CONFIG_PCI
Mingkai Hueee86ff2015-10-26 19:47:52 +0800118#define CONFIG_PCI_SCAN_SHOW
Mingkai Hueee86ff2015-10-26 19:47:52 +0800119#endif
Sumit Garg2a2857b2017-03-30 09:52:38 +0530120#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +0800121
Gong Qianyu51c18dc2016-01-25 15:16:05 +0800122/* DSPI */
Gong Qianyu51c18dc2016-01-25 15:16:05 +0800123
Shaohui Xie04643262015-10-26 19:47:54 +0800124/* FMan ucode */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530125#ifndef SPL_NO_FMAN
Shaohui Xie04643262015-10-26 19:47:54 +0800126#define CONFIG_SYS_DPAA_FMAN
127#ifdef CONFIG_SYS_DPAA_FMAN
128#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
129
Shaohui Xie04643262015-10-26 19:47:54 +0800130#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
131#endif
Sumit Garg2a2857b2017-03-30 09:52:38 +0530132#endif
Shaohui Xie04643262015-10-26 19:47:54 +0800133
Mingkai Hueee86ff2015-10-26 19:47:52 +0800134/* Miscellaneous configurable options */
Mingkai Hueee86ff2015-10-26 19:47:52 +0800135
136#define CONFIG_HWCONFIG
137#define HWCONFIG_BUFFER_SIZE 128
138
Sumit Garg2a2857b2017-03-30 09:52:38 +0530139#ifndef SPL_NO_MISC
Shengzhou Liu9d662542017-06-08 15:59:48 +0800140#ifndef CONFIG_SPL_BUILD
141#define BOOT_TARGET_DEVICES(func) \
142 func(MMC, mmc, 0) \
Mian Yousaf Kaukab6519df72019-01-29 16:38:40 +0100143 func(USB, usb, 0) \
144 func(DHCP, dhcp, na)
Shengzhou Liu9d662542017-06-08 15:59:48 +0800145#include <config_distro_bootcmd.h>
146#endif
147
Mingkai Hueee86ff2015-10-26 19:47:52 +0800148/* Initial environment variables */
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Hueee86ff2015-10-26 19:47:52 +0800151 "fdt_high=0xffffffffffffffff\0" \
152 "initrd_high=0xffffffffffffffff\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530153 "kernel_addr=0x61000000\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800154 "scriptaddr=0x80000000\0" \
Sumit Garg9cbcc4d2017-06-05 23:51:51 +0530155 "scripthdraddr=0x80080000\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800156 "fdtheader_addr_r=0x80100000\0" \
157 "kernelheader_addr_r=0x80200000\0" \
158 "kernel_addr_r=0x81000000\0" \
Wen He335b3862018-11-20 16:55:25 +0800159 "kernel_start=0x1000000\0" \
160 "kernelheader_start=0x800000\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800161 "fdt_addr_r=0x90000000\0" \
162 "load_addr=0xa0000000\0" \
Manish Tomar8d388012020-11-05 14:08:55 +0530163 "kernelheader_addr=0x60600000\0" \
Qianyu Gong2758edf2016-03-15 16:35:57 +0800164 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530165 "kernelheader_size=0x40000\0" \
Shengzhou Liu42862752017-11-09 17:57:55 +0800166 "kernel_addr_sd=0x8000\0" \
167 "kernel_size_sd=0x14000\0" \
Manish Tomar8d388012020-11-05 14:08:55 +0530168 "kernelhdr_addr_sd=0x3000\0" \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530169 "kernelhdr_size_sd=0x10\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800170 "console=ttyS0,115200\0" \
York Sunf7eed6b2017-09-28 08:42:16 -0700171 "boot_os=y\0" \
Tom Rini5ad8e112017-10-22 17:55:07 -0400172 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800173 BOOTENV \
174 "boot_scripts=ls1043ardb_boot.scr\0" \
Sumit Garg9cbcc4d2017-06-05 23:51:51 +0530175 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800176 "scan_dev_for_boot_part=" \
177 "part list ${devtype} ${devnum} devplist; " \
178 "env exists devplist || setenv devplist 1; " \
179 "for distro_bootpart in ${devplist}; do " \
180 "if fstype ${devtype} " \
181 "${devnum}:${distro_bootpart} " \
182 "bootfstype; then " \
183 "run scan_dev_for_boot; " \
184 "fi; " \
185 "done\0" \
Sumit Garg9cbcc4d2017-06-05 23:51:51 +0530186 "boot_a_script=" \
187 "load ${devtype} ${devnum}:${distro_bootpart} " \
188 "${scriptaddr} ${prefix}${script}; " \
189 "env exists secureboot && load ${devtype} " \
190 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai25355ec2019-04-23 05:52:17 +0000191 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
192 "env exists secureboot " \
Sumit Garg9cbcc4d2017-06-05 23:51:51 +0530193 "&& esbc_validate ${scripthdraddr};" \
194 "source ${scriptaddr}\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800195 "qspi_bootcmd=echo Trying load from qspi..;" \
196 "sf probe && sf read $load_addr " \
Wen Hecabe55c2019-11-14 15:08:15 +0800197 "$kernel_start $kernel_size; env exists secureboot " \
198 "&& sf read $kernelheader_addr_r $kernelheader_start " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530199 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
200 "bootm $load_addr#$board\0" \
Shengzhou Liu9d662542017-06-08 15:59:48 +0800201 "nor_bootcmd=echo Trying load from nor..;" \
202 "cp.b $kernel_addr $load_addr " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530203 "$kernel_size; env exists secureboot " \
204 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
205 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
206 "bootm $load_addr#$board\0" \
Wen He335b3862018-11-20 16:55:25 +0800207 "nand_bootcmd=echo Trying load from NAND..;" \
208 "nand info; nand read $load_addr " \
209 "$kernel_start $kernel_size; env exists secureboot " \
210 "&& nand read $kernelheader_addr_r $kernelheader_start " \
211 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
212 "bootm $load_addr#$board\0" \
Shengzhou Liu42862752017-11-09 17:57:55 +0800213 "sd_bootcmd=echo Trying load from SD ..;" \
214 "mmcinfo; mmc read $load_addr " \
215 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572230c6e10a2017-11-22 10:38:35 +0530216 "env exists secureboot && mmc read $kernelheader_addr_r " \
217 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
218 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu42862752017-11-09 17:57:55 +0800219 "bootm $load_addr#$board\0"
220
Wenbin Song1738ca72016-07-21 18:55:16 +0800221
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000222#ifdef CONFIG_TFABOOT
223#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
224 "env exists secureboot && esbc_halt;"
225#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
226 "env exists secureboot && esbc_halt;"
227#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
228 "env exists secureboot && esbc_halt;"
Pankit Garg69210722018-12-27 04:37:53 +0000229#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
230 "env exists secureboot && esbc_halt;"
Sumit Garg2a2857b2017-03-30 09:52:38 +0530231#endif
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000232#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +0800233
Mingkai Hueee86ff2015-10-26 19:47:52 +0800234#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
235
Simon Glass89e0a3a2017-05-17 08:23:10 -0600236#include <asm/arch/soc.h>
237
Mingkai Hueee86ff2015-10-26 19:47:52 +0800238#endif /* __LS1043A_COMMON_H */