blob: cb68c41babaee87cdf506862abe194abaab572fb [file] [log] [blame]
wdenkc12081a2004-03-23 20:18:25 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc12081a2004-03-23 20:18:25 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc12081a2004-03-23 20:18:25 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020015#undef CONFIG_SYS_RAMBOOT
wdenkc12081a2004-03-23 20:18:25 +000016
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21
22#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
23#define CONFIG_PM828 1 /* ...on a PM828 module */
Jon Loeligerf5ad3782005-07-23 10:37:35 -050024#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkc12081a2004-03-23 20:18:25 +000025
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020026#ifndef CONFIG_SYS_TEXT_BASE
27#define CONFIG_SYS_TEXT_BASE 0x40000000 /* Standard: boot 64-bit flash */
28#endif
29
wdenkc12081a2004-03-23 20:18:25 +000030#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
31
wdenkc12081a2004-03-23 20:18:25 +000032#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
33
Wolfgang Denk1baed662008-03-03 12:16:44 +010034#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkc12081a2004-03-23 20:18:25 +000035
36#undef CONFIG_BOOTARGS
37#define CONFIG_BOOTCOMMAND \
38 "bootp;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010039 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
40 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkc12081a2004-03-23 20:18:25 +000041 "bootm"
42
43/* enable I2C and select the hardware/software driver */
Heiko Schocher479a4cf2013-01-29 08:53:15 +010044#define CONFIG_SYS_I2C
45#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
46#define CONFIG_SYS_I2C_SOFT_SPEED 50000
47#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenkc12081a2004-03-23 20:18:25 +000048/*
49 * Software (bit-bang) I2C driver configuration
50 */
51#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
52#define I2C_ACTIVE (iop->pdir |= 0x00010000)
53#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
54#define I2C_READ ((iop->pdat & 0x00010000) != 0)
55#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
56 else iop->pdat &= ~0x00010000
57#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
58 else iop->pdat &= ~0x00020000
59#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
60
61
62#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenkc12081a2004-03-23 20:18:25 +000064
65/*
66 * select serial console configuration
67 *
68 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
69 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
70 * for SCC).
71 *
72 * if CONFIG_CONS_NONE is defined, then the serial console routines must
73 * defined elsewhere (for example, on the cogent platform, there are serial
74 * ports on the motherboard which are used for the serial console - see
75 * cogent/cma101/serial.[ch]).
76 */
77#define CONFIG_CONS_ON_SMC /* define if console on SMC */
78#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
79#undef CONFIG_CONS_NONE /* define if console on something else*/
80#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
81
82/*
83 * select ethernet configuration
84 *
85 * if CONFIG_ETHER_ON_SCC is selected, then
86 * - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
wdenkc12081a2004-03-23 20:18:25 +000087 *
88 * if CONFIG_ETHER_ON_FCC is selected, then
89 * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
wdenkc12081a2004-03-23 20:18:25 +000090 *
91 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger2517d972007-07-09 17:15:49 -050092 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkc12081a2004-03-23 20:18:25 +000093 */
wdenkc12081a2004-03-23 20:18:25 +000094#undef CONFIG_ETHER_NONE /* define if ether on something else */
95
96#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
97#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
98
99#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
100/*
101 * - Rx-CLK is CLK11
102 * - Tx-CLK is CLK10
103 */
104#define CONFIG_ETHER_ON_FCC1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200105# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
wdenkc12081a2004-03-23 20:18:25 +0000106#ifndef CONFIG_DB_CR826_J30x_ON
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
wdenkc12081a2004-03-23 20:18:25 +0000108#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
wdenkc12081a2004-03-23 20:18:25 +0000110#endif
111/*
112 * - Rx-CLK is CLK15
113 * - Tx-CLK is CLK14
114 */
115#define CONFIG_ETHER_ON_FCC2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
117# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
wdenkc12081a2004-03-23 20:18:25 +0000118/*
119 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
120 * - Enable Full Duplex in FSMR
121 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122# define CONFIG_SYS_CPMFCR_RAMTYPE 0
123# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenkc12081a2004-03-23 20:18:25 +0000124
125/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
126#define CONFIG_8260_CLKIN 100000000 /* in Hz */
127
128#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
129#define CONFIG_BAUDRATE 230400
130#else
131#define CONFIG_BAUDRATE 9600
132#endif
133
134#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkc12081a2004-03-23 20:18:25 +0000136
137#undef CONFIG_WATCHDOG /* watchdog disabled */
138
Jon Loeliger7846bb22007-07-09 21:31:24 -0500139/*
140 * BOOTP options
141 */
142#define CONFIG_BOOTP_SUBNETMASK
143#define CONFIG_BOOTP_GATEWAY
144#define CONFIG_BOOTP_HOSTNAME
145#define CONFIG_BOOTP_BOOTPATH
146#define CONFIG_BOOTP_BOOTFILESIZE
wdenkc12081a2004-03-23 20:18:25 +0000147
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500148
149/*
150 * Command line configuration.
151 */
152#include <config_cmd_default.h>
153
154#define CONFIG_CMD_BEDBUG
155#define CONFIG_CMD_DATE
156#define CONFIG_CMD_DHCP
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500157#define CONFIG_CMD_EEPROM
158#define CONFIG_CMD_I2C
159#define CONFIG_CMD_NFS
160#define CONFIG_CMD_SNTP
161
wdenkc12081a2004-03-23 20:18:25 +0000162#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000163#define CONFIG_PCI_INDIRECT_BRIDGE
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500164#define CONFIG_CMD_PCI
165#endif
wdenkc12081a2004-03-23 20:18:25 +0000166
wdenkc12081a2004-03-23 20:18:25 +0000167/*
168 * Miscellaneous configurable options
169 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_LONGHELP /* undef to save memory */
171#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500172#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc12081a2004-03-23 20:18:25 +0000174#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc12081a2004-03-23 20:18:25 +0000176#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
178#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
179#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc12081a2004-03-23 20:18:25 +0000180
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
182#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc12081a2004-03-23 20:18:25 +0000183
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkc12081a2004-03-23 20:18:25 +0000185
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc12081a2004-03-23 20:18:25 +0000187
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
wdenkc12081a2004-03-23 20:18:25 +0000189
190/*
191 * For booting Linux, the board info and command line data
192 * have to be in the first 8 MB of memory, since this is
193 * the maximum mapped by the Linux kernel during initialization.
194 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc12081a2004-03-23 20:18:25 +0000196
197/*-----------------------------------------------------------------------
198 * Flash and Boot ROM mapping
199 */
200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_BOOTROM_BASE 0xFF800000
202#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
203#define CONFIG_SYS_FLASH0_BASE 0x40000000
204#define CONFIG_SYS_FLASH0_SIZE 0x02000000
205#define CONFIG_SYS_DOC_BASE 0xFF800000
206#define CONFIG_SYS_DOC_SIZE 0x00100000
wdenkc12081a2004-03-23 20:18:25 +0000207
208
209/* Flash bank size (for preliminary settings)
210 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
wdenkc12081a2004-03-23 20:18:25 +0000212
213/*-----------------------------------------------------------------------
214 * FLASH organization
215 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
217#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
wdenkc12081a2004-03-23 20:18:25 +0000218
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
220#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenkc12081a2004-03-23 20:18:25 +0000221
222#if 0
223/* Start port with environment in flash; switch to EEPROM later */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200224#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200226#define CONFIG_ENV_SIZE 0x40000
227#define CONFIG_ENV_SECT_SIZE 0x40000
wdenkc12081a2004-03-23 20:18:25 +0000228#else
229/* Final version: environment in EEPROM */
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200230#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
232#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
233#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
234#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200235#define CONFIG_ENV_OFFSET 512
236#define CONFIG_ENV_SIZE (2048 - 512)
wdenkc12081a2004-03-23 20:18:25 +0000237#endif
238
239/*-----------------------------------------------------------------------
240 * Hard Reset Configuration Words
241 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenkc12081a2004-03-23 20:18:25 +0000243 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200244 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenkc12081a2004-03-23 20:18:25 +0000245 */
246#if defined(CONFIG_BOOT_ROM)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200247#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
wdenkc12081a2004-03-23 20:18:25 +0000248#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200249#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
wdenkc12081a2004-03-23 20:18:25 +0000250#endif
251
252/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200253#define CONFIG_SYS_HRCW_SLAVE1 0
254#define CONFIG_SYS_HRCW_SLAVE2 0
255#define CONFIG_SYS_HRCW_SLAVE3 0
256#define CONFIG_SYS_HRCW_SLAVE4 0
257#define CONFIG_SYS_HRCW_SLAVE5 0
258#define CONFIG_SYS_HRCW_SLAVE6 0
259#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkc12081a2004-03-23 20:18:25 +0000260
261/*-----------------------------------------------------------------------
262 * Internal Memory Mapped Register
263 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#define CONFIG_SYS_IMMR 0xF0000000
wdenkc12081a2004-03-23 20:18:25 +0000265
266/*-----------------------------------------------------------------------
267 * Definitions for initial stack pointer and data area (in DPRAM)
268 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200269#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200270#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200271#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200272#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc12081a2004-03-23 20:18:25 +0000273
274/*-----------------------------------------------------------------------
275 * Start addresses for the final memory configuration
276 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200277 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc12081a2004-03-23 20:18:25 +0000278 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
wdenkc12081a2004-03-23 20:18:25 +0000280 * is mapped at SDRAM_BASE2_PRELIM.
281 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200282#define CONFIG_SYS_SDRAM_BASE 0x00000000
283#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200284#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200285#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
286#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenkc12081a2004-03-23 20:18:25 +0000287
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200288#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
289# define CONFIG_SYS_RAMBOOT
wdenkc12081a2004-03-23 20:18:25 +0000290#endif
291
292#ifdef CONFIG_PCI
293#define CONFIG_PCI_PNP
294#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkc12081a2004-03-23 20:18:25 +0000296#endif
297
wdenkc12081a2004-03-23 20:18:25 +0000298/*-----------------------------------------------------------------------
299 * Cache Configuration
300 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeligercc1f0bb2007-07-08 14:49:44 -0500302#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc12081a2004-03-23 20:18:25 +0000304#endif
305
306/*-----------------------------------------------------------------------
307 * HIDx - Hardware Implementation-dependent Registers 2-11
308 *-----------------------------------------------------------------------
309 * HID0 also contains cache control - initially enable both caches and
310 * invalidate contents, then the final state leaves only the instruction
311 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
312 * but Soft reset does not.
313 *
314 * HID1 has only read-only information - nothing to set.
315 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200316#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenkc12081a2004-03-23 20:18:25 +0000317 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200318#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
319#define CONFIG_SYS_HID2 0
wdenkc12081a2004-03-23 20:18:25 +0000320
321/*-----------------------------------------------------------------------
322 * RMR - Reset Mode Register 5-5
323 *-----------------------------------------------------------------------
324 * turn on Checkstop Reset Enable
325 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200326#define CONFIG_SYS_RMR RMR_CSRE
wdenkc12081a2004-03-23 20:18:25 +0000327
328/*-----------------------------------------------------------------------
329 * BCR - Bus Configuration 4-25
330 *-----------------------------------------------------------------------
331 */
332
333#define BCR_APD01 0x10000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200334#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
wdenkc12081a2004-03-23 20:18:25 +0000335
336/*-----------------------------------------------------------------------
337 * SIUMCR - SIU Module Configuration 4-31
338 *-----------------------------------------------------------------------
339 */
340#if 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200341#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
wdenkc12081a2004-03-23 20:18:25 +0000342#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200343#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
wdenkc12081a2004-03-23 20:18:25 +0000344#endif
345
346
347/*-----------------------------------------------------------------------
348 * SYPCR - System Protection Control 4-35
349 * SYPCR can only be written once after reset!
350 *-----------------------------------------------------------------------
351 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
352 */
353#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200354#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenkc12081a2004-03-23 20:18:25 +0000355 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
356#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200357#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenkc12081a2004-03-23 20:18:25 +0000358 SYPCR_SWRI|SYPCR_SWP)
359#endif /* CONFIG_WATCHDOG */
360
361/*-----------------------------------------------------------------------
362 * TMCNTSC - Time Counter Status and Control 4-40
363 *-----------------------------------------------------------------------
364 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
365 * and enable Time Counter
366 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200367#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenkc12081a2004-03-23 20:18:25 +0000368
369/*-----------------------------------------------------------------------
370 * PISCR - Periodic Interrupt Status and Control 4-42
371 *-----------------------------------------------------------------------
372 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
373 * Periodic timer
374 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200375#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenkc12081a2004-03-23 20:18:25 +0000376
377/*-----------------------------------------------------------------------
378 * SCCR - System Clock Control 9-8
379 *-----------------------------------------------------------------------
380 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200381#define CONFIG_SYS_SCCR (SCCR_DFBRG00)
wdenkc12081a2004-03-23 20:18:25 +0000382
383/*-----------------------------------------------------------------------
384 * RCCR - RISC Controller Configuration 13-7
385 *-----------------------------------------------------------------------
386 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200387#define CONFIG_SYS_RCCR 0
wdenkc12081a2004-03-23 20:18:25 +0000388
389/*
390 * Init Memory Controller:
391 *
392 * Bank Bus Machine PortSz Device
393 * ---- --- ------- ------ ------
394 * 0 60x GPCM 64 bit FLASH
395 * 1 60x SDRAM 64 bit SDRAM
396 *
397 */
398
399 /* Initialize SDRAM on local bus
400 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200401#define CONFIG_SYS_INIT_LOCAL_SDRAM
wdenkc12081a2004-03-23 20:18:25 +0000402
403
404/* Minimum mask to separate preliminary
405 * address ranges for CS[0:2]
406 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200407#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
wdenkc12081a2004-03-23 20:18:25 +0000408
409/*
410 * we use the same values for 32 MB and 128 MB SDRAM
411 * refresh rate = 7.68 uS (100 MHz Bus Clock)
412 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200413#define CONFIG_SYS_MPTPR 0x2000
414#define CONFIG_SYS_PSRT 0x16
wdenkc12081a2004-03-23 20:18:25 +0000415
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200416#define CONFIG_SYS_MRS_OFFS 0x00000000
wdenkc12081a2004-03-23 20:18:25 +0000417
418
419#if defined(CONFIG_BOOT_ROM)
420/*
421 * Bank 0 - Boot ROM (8 bit wide)
422 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200423#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
wdenkc12081a2004-03-23 20:18:25 +0000424 BRx_PS_8 |\
425 BRx_MS_GPCM_P |\
426 BRx_V)
427
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200428#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
wdenkc12081a2004-03-23 20:18:25 +0000429 ORxG_CSNT |\
430 ORxG_ACS_DIV1 |\
431 ORxG_SCY_5_CLK |\
432 ORxG_EHTR |\
433 ORxG_TRLX)
434
435/*
436 * Bank 1 - Flash (64 bit wide)
437 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200438#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenkc12081a2004-03-23 20:18:25 +0000439 BRx_PS_64 |\
440 BRx_MS_GPCM_P |\
441 BRx_V)
442
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200443#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenkc12081a2004-03-23 20:18:25 +0000444 ORxG_CSNT |\
445 ORxG_ACS_DIV1 |\
446 ORxG_SCY_5_CLK |\
447 ORxG_EHTR |\
448 ORxG_TRLX)
449
450#else /* ! CONFIG_BOOT_ROM */
451
452/*
453 * Bank 0 - Flash (64 bit wide)
454 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200455#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenkc12081a2004-03-23 20:18:25 +0000456 BRx_PS_64 |\
457 BRx_MS_GPCM_P |\
458 BRx_V)
459
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200460#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenkc12081a2004-03-23 20:18:25 +0000461 ORxG_CSNT |\
462 ORxG_ACS_DIV1 |\
463 ORxG_SCY_5_CLK |\
464 ORxG_EHTR |\
465 ORxG_TRLX)
466
467/*
468 * Bank 1 - Disk-On-Chip
469 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200470#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
wdenkc12081a2004-03-23 20:18:25 +0000471 BRx_PS_8 |\
472 BRx_MS_GPCM_P |\
473 BRx_V)
474
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200475#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
wdenkc12081a2004-03-23 20:18:25 +0000476 ORxG_CSNT |\
477 ORxG_ACS_DIV1 |\
478 ORxG_SCY_5_CLK |\
479 ORxG_EHTR |\
480 ORxG_TRLX)
481
482#endif /* CONFIG_BOOT_ROM */
483
484/* Bank 2 - SDRAM
485 */
486
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200487#ifndef CONFIG_SYS_RAMBOOT
488#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenkc12081a2004-03-23 20:18:25 +0000489 BRx_PS_64 |\
490 BRx_MS_SDRAM_P |\
491 BRx_V)
492
493 /* SDRAM initialization values for 8-column chips
494 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200495#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
wdenkc12081a2004-03-23 20:18:25 +0000496 ORxS_BPD_4 |\
497 ORxS_ROWST_PBI0_A9 |\
498 ORxS_NUMR_12)
499
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200500#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
wdenkc12081a2004-03-23 20:18:25 +0000501 PSDMR_BSMA_A14_A16 |\
502 PSDMR_SDA10_PBI0_A10 |\
503 PSDMR_RFRC_7_CLK |\
504 PSDMR_PRETOACT_2W |\
505 PSDMR_ACTTORW_2W |\
506 PSDMR_LDOTOPRE_1C |\
507 PSDMR_WRC_1C |\
508 PSDMR_CL_2)
509
510 /* SDRAM initialization values for 9-column chips
511 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200512#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
wdenkc12081a2004-03-23 20:18:25 +0000513 ORxS_BPD_4 |\
514 ORxS_ROWST_PBI0_A7 |\
515 ORxS_NUMR_13)
516
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200517#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
wdenkc12081a2004-03-23 20:18:25 +0000518 PSDMR_BSMA_A13_A15 |\
519 PSDMR_SDA10_PBI0_A9 |\
520 PSDMR_RFRC_7_CLK |\
521 PSDMR_PRETOACT_2W |\
522 PSDMR_ACTTORW_2W |\
523 PSDMR_LDOTOPRE_1C |\
524 PSDMR_WRC_1C |\
525 PSDMR_CL_2)
526
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200527#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL
528#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL
wdenkc12081a2004-03-23 20:18:25 +0000529
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200530#endif /* CONFIG_SYS_RAMBOOT */
wdenkc12081a2004-03-23 20:18:25 +0000531
532#endif /* __CONFIG_H */