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wdenk70ae5b42004-10-10 17:05:18 +00001/*
2 * i2c Support for Atmel's AT91RM9200 Two-Wire Interface
3 *
4 * (c) Rick Bronson
5 *
6 * Borrowed heavily from original work by:
7 * Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
8 *
9 * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25*/
26#include <common.h>
27
28#ifdef CONFIG_HARD_I2C
29
30#include <i2c.h>
31#include <asm/io.h>
32#include <asm/arch/hardware.h>
33
34#include <at91rm9200_i2c.h>
35
wdenk0598d202004-12-14 23:28:24 +000036/* define DEBUG */
wdenk70ae5b42004-10-10 17:05:18 +000037
38/*
39 * Poll the i2c status register until the specified bit is set.
40 * Returns 0 if timed out (100 msec)
41 */
42static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
43 int loop_cntr = 10000;
44 do {
wdenk20dd2fa2004-11-21 00:06:33 +000045 udelay(10);
wdenk70ae5b42004-10-10 17:05:18 +000046 } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
47
48 return (loop_cntr > 0);
49}
50
51/*
52 * Generic i2c master transfer entrypoint
53 *
54 * rw == 1 means that this is a read
55 */
56static int
57at91_xfer(unsigned char chip, unsigned int addr, int alen,
58 unsigned char *buffer, int len, int rw)
59{
60 AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
61 int length;
62 unsigned char *buf;
wdenk70ae5b42004-10-10 17:05:18 +000063 /* Set the TWI Master Mode Register */
64 twi->TWI_MMR = (chip << 16) | (alen << 8)
65 | ((rw == 1) ? AT91C_TWI_MREAD : 0);
66
67 /* Set TWI Internal Address Register with first messages data field */
68 /* only one address byte is supported */
69 if (alen > 0)
70 twi->TWI_IADR = addr & 0xff;
71
72 length = len;
73 buf = buffer;
74 if (length && buf) { /* sanity check */
75 if (rw) {
76 twi->TWI_CR = AT91C_TWI_START;
77 while (length--) {
78 if (!length)
79 twi->TWI_CR = AT91C_TWI_STOP;
80 /* Wait until transfer is finished */
81 if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
wdenk0598d202004-12-14 23:28:24 +000082 debug ("at91_i2c: timeout 1\n");
wdenk70ae5b42004-10-10 17:05:18 +000083 return 1;
84 }
85 *buf++ = twi->TWI_RHR;
86 }
87 if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
wdenk0598d202004-12-14 23:28:24 +000088 debug ("at91_i2c: timeout 2\n");
wdenk70ae5b42004-10-10 17:05:18 +000089 return 1;
90 }
91 } else {
92 twi->TWI_CR = AT91C_TWI_START;
93 while (length--) {
94 twi->TWI_THR = *buf++;
95 if (!length)
96 twi->TWI_CR = AT91C_TWI_STOP;
97 if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
wdenk0598d202004-12-14 23:28:24 +000098 debug ("at91_i2c: timeout 3\n");
wdenk70ae5b42004-10-10 17:05:18 +000099 return 1;
100 }
101 }
102 /* Wait until transfer is finished */
103 if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
wdenk0598d202004-12-14 23:28:24 +0000104 debug ("at91_i2c: timeout 4\n");
wdenk70ae5b42004-10-10 17:05:18 +0000105 return 1;
106 }
107 }
108 }
109 return 0;
110}
111
112int
113i2c_probe(unsigned char chip)
114{
115 char buffer[1];
116
117 return at91_xfer(chip, 0, 0, buffer, 1, 1);
118}
119
120int
wdenk27fa5852005-04-03 14:18:51 +0000121i2c_read (unsigned char chip, unsigned int addr, int alen,
122 unsigned char *buffer, int len)
wdenk70ae5b42004-10-10 17:05:18 +0000123{
wdenkcbb52882004-10-10 18:03:33 +0000124#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
wdenk70ae5b42004-10-10 17:05:18 +0000125 /* we only allow one address byte */
126 if (alen > 1)
127 return 1;
wdenk70ae5b42004-10-10 17:05:18 +0000128 /* XXX assume an ATMEL AT24C16 */
129 if (alen == 1) {
wdenkcbb52882004-10-10 18:03:33 +0000130#if 0 /* EEPROM code already sets this correctly */
wdenk70ae5b42004-10-10 17:05:18 +0000131 chip |= (addr >> 8) & 0xff;
wdenkcbb52882004-10-10 18:03:33 +0000132#endif
wdenk70ae5b42004-10-10 17:05:18 +0000133 addr = addr & 0xff;
134 }
135#endif
136 return at91_xfer(chip, addr, alen, buffer, len, 1);
137}
138
139int
140i2c_write(unsigned char chip, unsigned int addr, int alen,
wdenkd0245fc2005-04-13 10:02:42 +0000141 unsigned char *buffer, int len)
wdenk70ae5b42004-10-10 17:05:18 +0000142{
wdenkd0245fc2005-04-13 10:02:42 +0000143#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
wdenk70ae5b42004-10-10 17:05:18 +0000144 int i;
145 unsigned char *buf;
146
147 /* we only allow one address byte */
148 if (alen > 1)
149 return 1;
wdenk70ae5b42004-10-10 17:05:18 +0000150 /* XXX assume an ATMEL AT24C16 */
151 if (alen == 1) {
152 buf = buffer;
153 /* do single byte writes */
154 for (i = 0; i < len; i++) {
wdenkcbb52882004-10-10 18:03:33 +0000155#if 0 /* EEPROM code already sets this correctly */
wdenk70ae5b42004-10-10 17:05:18 +0000156 chip |= (addr >> 8) & 0xff;
wdenkcbb52882004-10-10 18:03:33 +0000157#endif
wdenk70ae5b42004-10-10 17:05:18 +0000158 addr = addr & 0xff;
159 if (at91_xfer(chip, addr, alen, buf++, 1, 0))
160 return 1;
wdenkcbb52882004-10-10 18:03:33 +0000161 addr++;
wdenk70ae5b42004-10-10 17:05:18 +0000162 }
wdenkcbb52882004-10-10 18:03:33 +0000163 return 0;
wdenk70ae5b42004-10-10 17:05:18 +0000164 }
wdenk70ae5b42004-10-10 17:05:18 +0000165#endif
166 return at91_xfer(chip, addr, alen, buffer, len, 0);
167}
168
169/*
170 * Main initialization routine
171 */
172void
173i2c_init(int speed, int slaveaddr)
174{
175 AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
176
177 *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
178 *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
179 *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;
180 *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */
181
182 twi->TWI_IDR = 0x3ff; /* Disable all interrupts */
183 twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */
184 twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */
185
186 /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
187 twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
188
wdenk0598d202004-12-14 23:28:24 +0000189 debug ("Found AT91 i2c\n");
wdenk70ae5b42004-10-10 17:05:18 +0000190 return;
191}
wdenk10164c62005-04-07 22:36:40 +0000192
193uchar i2c_reg_read(uchar i2c_addr, uchar reg)
194{
195 char buf;
196
197 i2c_read(i2c_addr, reg, 1, &buf, 1);
198
199 return(buf);
200}
201
202void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
203{
204 i2c_write(i2c_addr, reg, 1, &val, 1);
205}
206
wdenk70ae5b42004-10-10 17:05:18 +0000207#endif /* CONFIG_HARD_I2C */