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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Beniamino Galvani2176d732016-08-16 11:49:49 +02002/*
3 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
Beniamino Galvani2176d732016-08-16 11:49:49 +02004 */
5
6#ifndef __PINCTRL_MESON_H__
7#define __PINCTRL_MESON_H__
8
9#include <linux/types.h>
10
11struct meson_pmx_group {
12 const char *name;
13 const unsigned int *pins;
14 unsigned int num_pins;
Jerome Brunet707bff42018-10-05 09:35:26 +020015 const void *data;
Beniamino Galvani2176d732016-08-16 11:49:49 +020016};
17
18struct meson_pmx_func {
19 const char *name;
20 const char * const *groups;
21 unsigned int num_groups;
22};
23
24struct meson_pinctrl_data {
25 const char *name;
26 struct meson_pmx_group *groups;
27 struct meson_pmx_func *funcs;
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020028 struct meson_bank *banks;
Beniamino Galvani2176d732016-08-16 11:49:49 +020029 unsigned int pin_base;
30 unsigned int num_pins;
31 unsigned int num_groups;
32 unsigned int num_funcs;
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020033 unsigned int num_banks;
Jerome Brunet707bff42018-10-05 09:35:26 +020034 const struct driver *gpio_driver;
35 void *pmx_data;
Beniamino Galvani2176d732016-08-16 11:49:49 +020036};
37
38struct meson_pinctrl {
39 struct meson_pinctrl_data *data;
40 void __iomem *reg_mux;
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020041 void __iomem *reg_gpio;
Jerome Brunet87021992019-01-04 15:44:34 +010042 void __iomem *reg_pull;
43 void __iomem *reg_pullen;
Jerome Brunet0ff3cd02019-02-08 17:40:57 +010044 void __iomem *reg_ds;
Beniamino Galvani2176d732016-08-16 11:49:49 +020045};
46
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020047/**
48 * struct meson_reg_desc - a register descriptor
49 *
50 * @reg: register offset in the regmap
51 * @bit: bit index in register
52 *
53 * The structure describes the information needed to control pull,
54 * pull-enable, direction, etc. for a single pin
55 */
56struct meson_reg_desc {
57 unsigned int reg;
58 unsigned int bit;
59};
60
61/**
Guillaume La Roque30767352019-06-04 13:53:07 +020062 * enum meson_pinconf_drv - value of drive-strength supported
63 */
64enum meson_pinconf_drv {
65 MESON_PINCONF_DRV_500UA,
66 MESON_PINCONF_DRV_2500UA,
67 MESON_PINCONF_DRV_3000UA,
68 MESON_PINCONF_DRV_4000UA,
69};
70
71/**
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020072 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
73 */
74enum meson_reg_type {
75 REG_PULLEN,
76 REG_PULL,
77 REG_DIR,
78 REG_OUT,
79 REG_IN,
Guillaume La Roque30767352019-06-04 13:53:07 +020080 REG_DS,
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020081 NUM_REG,
82};
83
84/**
85 * struct meson bank
86 *
87 * @name: bank name
88 * @first: first pin of the bank
89 * @last: last pin of the bank
90 * @regs: array of register descriptors
91 *
92 * A bank represents a set of pins controlled by a contiguous set of
93 * bits in the domain registers. The structure specifies which bits in
94 * the regmap control the different functionalities. Each member of
95 * the @regs array refers to the first pin of the bank.
96 */
97struct meson_bank {
98 const char *name;
99 unsigned int first;
100 unsigned int last;
101 struct meson_reg_desc regs[NUM_REG];
102};
103
Beniamino Galvani2176d732016-08-16 11:49:49 +0200104#define PIN(x, b) (b + x)
105
Beniamino Galvani2176d732016-08-16 11:49:49 +0200106#define FUNCTION(fn) \
107 { \
108 .name = #fn, \
109 .groups = fn ## _groups, \
110 .num_groups = ARRAY_SIZE(fn ## _groups), \
111 }
112
Guillaume La Roque30767352019-06-04 13:53:07 +0200113#define BANK_DS(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib, \
114 dsr, dsb) \
115 { \
116 .name = n, \
117 .first = f, \
118 .last = l, \
119 .regs = { \
120 [REG_PULLEN] = {per, peb}, \
121 [REG_PULL] = {pr, pb}, \
122 [REG_DIR] = {dr, db}, \
123 [REG_OUT] = { or, ob}, \
124 [REG_IN] = {ir, ib}, \
125 [REG_DS] = {dsr, dsb}, \
126 }, \
127 }
128
129#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
130 BANK_DS(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0)
Beniamino Galvani5aeb1352017-07-10 00:30:04 +0200131
Beniamino Galvani2176d732016-08-16 11:49:49 +0200132#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
133
134extern const struct pinctrl_ops meson_pinctrl_ops;
135
Jerome Brunet707bff42018-10-05 09:35:26 +0200136int meson_pinctrl_get_groups_count(struct udevice *dev);
137const char *meson_pinctrl_get_group_name(struct udevice *dev,
138 unsigned int selector);
Neil Armstronga5ea1572019-06-04 11:04:52 +0200139int meson_pinctrl_get_pins_count(struct udevice *dev);
140const char *meson_pinctrl_get_pin_name(struct udevice *dev,
141 unsigned int selector);
Jerome Brunet707bff42018-10-05 09:35:26 +0200142int meson_pinmux_get_functions_count(struct udevice *dev);
143const char *meson_pinmux_get_function_name(struct udevice *dev,
144 unsigned int selector);
Beniamino Galvani2176d732016-08-16 11:49:49 +0200145int meson_pinctrl_probe(struct udevice *dev);
146
Jerome Brunet707bff42018-10-05 09:35:26 +0200147int meson_gpio_get(struct udevice *dev, unsigned int offset);
148int meson_gpio_set(struct udevice *dev, unsigned int offset, int value);
149int meson_gpio_get_direction(struct udevice *dev, unsigned int offset);
150int meson_gpio_direction_input(struct udevice *dev, unsigned int offset);
151int meson_gpio_direction_output(struct udevice *dev, unsigned int offset,
152 int value);
153int meson_gpio_probe(struct udevice *dev);
154
Jerome Brunet87021992019-01-04 15:44:34 +0100155int meson_pinconf_set(struct udevice *dev, unsigned int pin,
156 unsigned int param, unsigned int arg);
157int meson_pinconf_group_set(struct udevice *dev,
158 unsigned int group_selector,
159 unsigned int param, unsigned int arg);
160
Beniamino Galvani2176d732016-08-16 11:49:49 +0200161#endif /* __PINCTRL_MESON_H__ */