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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Beniamino Galvani2176d732016-08-16 11:49:49 +02002/*
3 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
Beniamino Galvani2176d732016-08-16 11:49:49 +02004 */
5
6#ifndef __PINCTRL_MESON_H__
7#define __PINCTRL_MESON_H__
8
9#include <linux/types.h>
10
11struct meson_pmx_group {
12 const char *name;
13 const unsigned int *pins;
14 unsigned int num_pins;
15 bool is_gpio;
16 unsigned int reg;
17 unsigned int bit;
18};
19
20struct meson_pmx_func {
21 const char *name;
22 const char * const *groups;
23 unsigned int num_groups;
24};
25
26struct meson_pinctrl_data {
27 const char *name;
28 struct meson_pmx_group *groups;
29 struct meson_pmx_func *funcs;
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020030 struct meson_bank *banks;
Beniamino Galvani2176d732016-08-16 11:49:49 +020031 unsigned int pin_base;
32 unsigned int num_pins;
33 unsigned int num_groups;
34 unsigned int num_funcs;
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020035 unsigned int num_banks;
Beniamino Galvani2176d732016-08-16 11:49:49 +020036};
37
38struct meson_pinctrl {
39 struct meson_pinctrl_data *data;
40 void __iomem *reg_mux;
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020041 void __iomem *reg_gpio;
Beniamino Galvani2176d732016-08-16 11:49:49 +020042};
43
Beniamino Galvani5aeb1352017-07-10 00:30:04 +020044/**
45 * struct meson_reg_desc - a register descriptor
46 *
47 * @reg: register offset in the regmap
48 * @bit: bit index in register
49 *
50 * The structure describes the information needed to control pull,
51 * pull-enable, direction, etc. for a single pin
52 */
53struct meson_reg_desc {
54 unsigned int reg;
55 unsigned int bit;
56};
57
58/**
59 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
60 */
61enum meson_reg_type {
62 REG_PULLEN,
63 REG_PULL,
64 REG_DIR,
65 REG_OUT,
66 REG_IN,
67 NUM_REG,
68};
69
70/**
71 * struct meson bank
72 *
73 * @name: bank name
74 * @first: first pin of the bank
75 * @last: last pin of the bank
76 * @regs: array of register descriptors
77 *
78 * A bank represents a set of pins controlled by a contiguous set of
79 * bits in the domain registers. The structure specifies which bits in
80 * the regmap control the different functionalities. Each member of
81 * the @regs array refers to the first pin of the bank.
82 */
83struct meson_bank {
84 const char *name;
85 unsigned int first;
86 unsigned int last;
87 struct meson_reg_desc regs[NUM_REG];
88};
89
Beniamino Galvani2176d732016-08-16 11:49:49 +020090#define PIN(x, b) (b + x)
91
92#define GROUP(grp, r, b) \
93 { \
94 .name = #grp, \
95 .pins = grp ## _pins, \
96 .num_pins = ARRAY_SIZE(grp ## _pins), \
97 .reg = r, \
98 .bit = b, \
99 }
100
101#define GPIO_GROUP(gpio, b) \
102 { \
103 .name = #gpio, \
104 .pins = (const unsigned int[]){ PIN(gpio, b) }, \
105 .num_pins = 1, \
106 .is_gpio = true, \
107 }
108
109#define FUNCTION(fn) \
110 { \
111 .name = #fn, \
112 .groups = fn ## _groups, \
113 .num_groups = ARRAY_SIZE(fn ## _groups), \
114 }
115
Beniamino Galvani5aeb1352017-07-10 00:30:04 +0200116#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
117 { \
118 .name = n, \
119 .first = f, \
120 .last = l, \
121 .regs = { \
122 [REG_PULLEN] = { per, peb }, \
123 [REG_PULL] = { pr, pb }, \
124 [REG_DIR] = { dr, db }, \
125 [REG_OUT] = { or, ob }, \
126 [REG_IN] = { ir, ib }, \
127 }, \
128 }
129
Beniamino Galvani2176d732016-08-16 11:49:49 +0200130#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
131
132extern const struct pinctrl_ops meson_pinctrl_ops;
133
134int meson_pinctrl_probe(struct udevice *dev);
135
136#endif /* __PINCTRL_MESON_H__ */